From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 42C9A34BA3B; Mon, 26 Jan 2026 17:22:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769448158; cv=none; b=GPjjDsggGzkJHhiIBEx+SFpaYNDdtXCeiT7DLodm50lzkCPCYf991qpOQqjpx0mnsyZ3WOL5QxBpjezz+eDc8evCOnW+Y/Vb0bk+ZpRlGCLTW3EBi/eC+3ULt9WlTG18WRQ1/iB+401bTmXfRcAAS7ALtVy1d7ZumI76hVvnvdU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769448158; c=relaxed/simple; bh=eghqj92Y52D4V4ClHuluYZDfNgx5ZgHZuwhcBbksV7Q=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=UZGeIWQh+SRtFQEyhz32HJJZJciYafqbRMmZcYEA1oRODGoGwjtGclyMEF5/3PE7RhU3USfI6Qw2AHjiNAJtnati8A5kOQ4jGNuQduwjQAP5m3RpYLUnFpN0JzRlc+vjauIxtb/lZXgFFMe3ZlrsvcbjBVw6rQCGW2ChJxxKHs4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 73657497; Mon, 26 Jan 2026 09:22:27 -0800 (PST) Received: from [10.57.68.157] (unknown [10.57.68.157]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6FB293F5CA; Mon, 26 Jan 2026 09:22:31 -0800 (PST) Message-ID: Date: Mon, 26 Jan 2026 17:22:29 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU Content-Language: en-GB To: Jie Gan , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Mao Jinlong , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski References: <20260122-enable-byte-cntr-for-ctcu-v10-0-22978e3c169f@oss.qualcomm.com> <20260122-enable-byte-cntr-for-ctcu-v10-5-22978e3c169f@oss.qualcomm.com> From: Suzuki K Poulose In-Reply-To: <20260122-enable-byte-cntr-for-ctcu-v10-5-22978e3c169f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 22/01/2026 02:08, Jie Gan wrote: > Add an interrupt property to CTCU device. The interrupt will be triggered > when the data size in the ETR buffer exceeds the threshold of the > BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register > of CTCU device will enable the interrupt. > > Acked-by: Krzysztof Kozlowski > Reviewed-by: Mike Leach > Signed-off-by: Jie Gan > --- > Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > index c969c16c21ef..ac27a8b89085 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > @@ -39,6 +39,11 @@ properties: > items: > - const: apb > > + interrupts: > + items: > + - description: Interrupt for the ETR device connected to in-port0. > + - description: Interrupt for the ETR device connected to in-port1. Is this all the hardware supports ? i.e., can it only have two ports ever ? If not, why restrict it to two ? Suzuki > + > label: > description: > Description of a coresight device. > @@ -60,6 +65,8 @@ additionalProperties: false > > examples: > - | > + #include > + > ctcu@1001000 { > compatible = "qcom,sa8775p-ctcu"; > reg = <0x1001000 0x1000>; > @@ -67,6 +74,9 @@ examples: > clocks = <&aoss_qmp>; > clock-names = "apb"; > > + interrupts = , > + ; > + > in-ports { > #address-cells = <1>; > #size-cells = <0>; >