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Wed, 11 Mar 2026 01:37:29 -0700 (PDT) X-Received: by 2002:a05:6a00:349a:b0:81f:4e1c:1d3b with SMTP id d2e1a72fcca58-829f7ae6a79mr1535869b3a.23.1773218248955; Wed, 11 Mar 2026 01:37:28 -0700 (PDT) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829f6df3b14sm1736918b3a.20.2026.03.11.01.37.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Mar 2026 01:37:28 -0700 (PDT) Message-ID: Date: Wed, 11 Mar 2026 14:07:18 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 0/4] PCI: Add support for resetting the Root Ports in a platform specific way To: manivannan.sadhasivam@oss.qualcomm.com, Bjorn Helgaas , Mahesh J Salgaonkar , Oliver O'Halloran , Will Deacon , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Heiko Stuebner , Philipp Zabel Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Niklas Cassel , Wilfred Mallawa , Lukas Wunner , Richard Zhu , Brian Norris , Wilson Ding , Frank Li References: <20260310-pci-port-reset-v7-0-9dd00ccc25ab@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20260310-pci-port-reset-v7-0-9dd00ccc25ab@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDA3MSBTYWx0ZWRfX8h0LPyBv9/nQ NUJVdB/sLDRKTTWV8LK2mNkKLSMpzk+S3XdPYje4TLKDr1gwrgx6mlYAHqXTZM8AY3N1IEeSkZS ydyWXD5ySnFA96zFoj3Sc+TxeLeO1lIBXzCh1Yrh/zlyCritanRmigDz+Xlw+7X/cFciUrdnuTK 4kR4tIqONR4GAaywluXn9wUxhnJeRg/B9/QEQtc/l+bMKIqdhP8rtx/0Fq+p9k7mXj4ovzuDTmP LB6U+dt5ySvIEgnM1TfkpZLU7ROLTWhhdWHzYKy1d5qxjqXOwvgxtU4raOV8gze/nVqdJgL+RQo yIwQiFDb3NDzlbFndjcgViA94S3pk/64YwcsczOVHbI+9xsoHpo8Qj4TGDi5rq7++WX6fsuwcAn 3eHovOS9RIbYXIme93g+rbaH4GCqIJILeG7AgHdSgO+CyfbKZueMrEVpv1VuctkbF4zvRRrVFTc rIny/Ps4jg1nQ46j1jw== X-Authority-Analysis: v=2.4 cv=O/U0fR9W c=1 sm=1 tr=0 ts=69b129ca cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=lJ8DZ0MjVbnDIa4D:21 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=ImqNvw3yTObJCdT6Mg8A:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: aWdZSRVSFrZgn_xBhjMCBAdCdREeVSoe X-Proofpoint-ORIG-GUID: aWdZSRVSFrZgn_xBhjMCBAdCdREeVSoe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-11_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 phishscore=0 impostorscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 spamscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110071 On 3/10/2026 7:31 PM, Manivannan Sadhasivam via B4 Relay wrote: > Hi, > > Currently, in the event of AER/DPC, PCI core will try to reset the slot (Root > Port) and its subordinate devices by invoking bridge control reset and FLR. But > in some cases like AER Fatal error, it might be necessary to reset the Root > Ports using the PCI host bridge drivers in a platform specific way (as indicated > by the TODO in the pcie_do_recovery() function in drivers/pci/pcie/err.c). > Otherwise, the PCI link won't be recovered successfully. > > So this series adds a new callback 'pci_host_bridge::reset_root_port' for the > host bridge drivers to reset the Root Port when a fatal error happens. > > Also, this series allows the host bridge drivers to handle PCI link down event > by resetting the Root Ports and recovering the bus. This is accomplished by the > help of the new 'pci_host_handle_link_down()' API. Host bridge drivers are > expected to call this API (preferrably from a threaded IRQ handler) with > relevant Root Port 'pci_dev' when a link down event is detected for the port. > The API will reuse the pcie_do_recovery() function to recover the link if AER > support is enabled, otherwise it will directly call the reset_root_port() > callback of the host bridge driver (if exists). > > For reference, I've modified the pcie-qcom driver to call > pci_host_handle_link_down() API with Root Port 'pci_dev' after receiving the > LDn global_irq event and populated 'pci_host_bridge::reset_root_port()' > callback to reset the Root Ports. > > Testing > ------- > > Tested on Qcom Lemans AU Ride platform with Host and EP SoCs connected over PCIe > link. Simulated the LDn by disabling LTSSM_EN on the EP and I could verify that > the link was getting recovered successfully. > > Changes in v7: > - Dropped Rockchip Root port reset patch due to reported issues. But the series > works on other platforms as tested by others. > - Added pci_{lock/unlock}_rescan_remove() to guard pci_bus_error_reset() as the > device could be removed in-between due to Native hotplug interrupt. > - Rebased on top of v7.0-rc1 > - Link to v6: https://lore.kernel.org/r/20250715-pci-port-reset-v6-0-6f9cce94e7bb@oss.qualcomm.com > > Changes in v6: > - Incorporated the patch: https://lore.kernel.org/all/20250524185304.26698-2-manivannan.sadhasivam@linaro.org/ > - Link to v5: https://lore.kernel.org/r/20250715-pci-port-reset-v5-0-26a5d278db40@oss.qualcomm.com > > Changes in v5: > * Reworked the pci_host_handle_link_down() to accept Root Port instead of > resetting all Root Ports in the event of link down. > * Renamed 'reset_slot' to 'reset_root_port' to avoid confusion as both terms > were used interchangibly and the series is intended to reset Root Port only. > * Added the Rockchip driver change to this series. > * Dropped the applied patches and review/tested tags due to rework. > * Rebased on top of v6.16-rc1. > > Changes in v4: > - Handled link down first in the irq handler > - Updated ICC & OPP bandwidth after link up in reset_slot() callback > - Link to v3: https://lore.kernel.org/r/20250417-pcie-reset-slot-v3-0-59a10811c962@linaro.org > > Changes in v3: > - Made the pci-host-common driver as a common library for host controller > drivers > - Moved the reset slot code to pci-host-common library > - Link to v2: https://lore.kernel.org/r/20250416-pcie-reset-slot-v2-0-efe76b278c10@linaro.org > > Changes in v2: > - Moved calling reset_slot() callback from pcie_do_recovery() to pcibios_reset_secondary_bus() > - Link to v1: https://lore.kernel.org/r/20250404-pcie-reset-slot-v1-0-98952918bf90@linaro.org > > Signed-off-by: Manivannan Sadhasivam For entire series, Reviewed-by: Krishna Chaitanya Chundru - Krishna Chaitanya. > --- > Manivannan Sadhasivam (4): > PCI/ERR: Add support for resetting the Root Ports in a platform specific way > PCI: host-common: Add link down handling for Root Ports > PCI: qcom: Add support for resetting the Root Port due to link down event > misc: pci_endpoint_test: Add AER error handlers > > drivers/misc/pci_endpoint_test.c | 20 +++++ > drivers/pci/controller/dwc/pcie-qcom.c | 143 ++++++++++++++++++++++++++++++- > drivers/pci/controller/pci-host-common.c | 35 ++++++++ > drivers/pci/controller/pci-host-common.h | 1 + > drivers/pci/pci.c | 21 +++++ > drivers/pci/pcie/err.c | 6 +- > include/linux/pci.h | 1 + > 7 files changed, 221 insertions(+), 6 deletions(-) > --- > base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f > change-id: 20250715-pci-port-reset-4d9519570123 > > Best regards,