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([2a01:e0a:106d:1080:9df2:2e39:58f0:72ca]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-492fc80e017sm2563298f8f.34.2026.11.06.02.52.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Nov 2026 02:52:55 -0800 (PST) Message-ID: Date: Fri, 6 Nov 2026 11:52:54 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCH 02/10] arm64: dts: amlogic: meson-s4: describe the CPU caches To: christian.koever-draxl@student.uibk.ac.at, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, =?UTF-8?Q?Christian_Stefan_K=C3=B6v=C3=A9r-Draxl?= References: <20261106104659.54656-1-christian.koever-draxl@student.uibk.ac.at> <20261106104659.54656-3-christian.koever-draxl@student.uibk.ac.at> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 11/6/26 11:46, christian.koever-draxl@student.uibk.ac.at wrote: > From: Christian Stefan Kövér-Draxl > > Describe the per-core L1 caches and the shared 512 KiB L2 cache, with > the geometry the cores report in CCSIDR_EL1 on an S905W2. > > Signed-off-by: Christian Stefan Kövér-Draxl > --- > arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 38 +++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi > index 2a6fbd530836..675db02a8d5e 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi > @@ -22,6 +22,13 @@ cpu0: cpu@0 { > compatible = "arm,cortex-a35"; > reg = <0x0 0x0>; > enable-method = "psci"; > + d-cache-line-size = <64>; > + d-cache-size = <0x8000>; > + d-cache-sets = <128>; > + i-cache-line-size = <64>; > + i-cache-size = <0x8000>; > + i-cache-sets = <256>; > + next-level-cache = <&l2>; > }; > > cpu1: cpu@1 { > @@ -29,6 +36,13 @@ cpu1: cpu@1 { > compatible = "arm,cortex-a35"; > reg = <0x0 0x1>; > enable-method = "psci"; > + d-cache-line-size = <64>; > + d-cache-size = <0x8000>; > + d-cache-sets = <128>; > + i-cache-line-size = <64>; > + i-cache-size = <0x8000>; > + i-cache-sets = <256>; > + next-level-cache = <&l2>; > }; > > cpu2: cpu@2 { > @@ -36,6 +50,13 @@ cpu2: cpu@2 { > compatible = "arm,cortex-a35"; > reg = <0x0 0x2>; > enable-method = "psci"; > + d-cache-line-size = <64>; > + d-cache-size = <0x8000>; > + d-cache-sets = <128>; > + i-cache-line-size = <64>; > + i-cache-size = <0x8000>; > + i-cache-sets = <256>; > + next-level-cache = <&l2>; > }; > > cpu3: cpu@3 { > @@ -43,6 +64,23 @@ cpu3: cpu@3 { > compatible = "arm,cortex-a35"; > reg = <0x0 0x3>; > enable-method = "psci"; > + d-cache-line-size = <64>; > + d-cache-size = <0x8000>; > + d-cache-sets = <128>; > + i-cache-line-size = <64>; > + i-cache-size = <0x8000>; > + i-cache-sets = <256>; > + next-level-cache = <&l2>; > + }; > + > + /* Geometry as CCSIDR_EL1 reports it on S905W2. */ > + l2: l2-cache0 { > + compatible = "cache"; > + cache-level = <2>; > + cache-unified; > + cache-size = <0x80000>; /* L2. 512 KB */ > + cache-line-size = <64>; > + cache-sets = <1024>; > }; > }; > Reviewed-by: Neil Armstrong Thanks, Neil