From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F330B274FD0 for ; Wed, 1 Jul 2026 13:57:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782914225; cv=none; b=KRBhR0XQM9HB9f35j3NC+b8HkuF3gapD6w3Sbaqh0mWkKQXWeNY2a3R/2owsK//WKO8Bz95IdTb1HcNmUOvwkaV8ISo/lqmm4UHvAbtGUMO9JpCmkhuYBYuJtDTHJF903Oys/4XsIl5fmcO3jy57mrzu6mX8fztKGVlblG3FxbM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782914225; c=relaxed/simple; bh=mVLT/bZtmsvDP8l2z/Ofu3piyv4ESpctt264BB4HIGE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=shmekI5Y9BNjZu6BA3QcdiSb7f0U3/hiTQ5Y9O4epmRdqrJYJY6tdqbX5Aujw+YWwGSUYobX5o5JaCFf3R51rwGlD2nNBOmQe13ekY5BNlf9fShc9+WlRs3ms4oDsRxQg9nfV+gpL9fEHJsP1ZjX1UjZS/rnn1mZRcrpJxx1YWg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JqUexwgd; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JqUexwgd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782914224; x=1814450224; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mVLT/bZtmsvDP8l2z/Ofu3piyv4ESpctt264BB4HIGE=; b=JqUexwgdxPQyRiRU1nZuxe26OvzYb2vdBh2uM8hAgED03iCB/cYZrej1 5Gb/8pSx7dV247LAk4ZRLzpOcTTRnTSkbSJmRvmnfkPwM+lVM7F/Yp+gu 5GoeDLs7V+2lqpq5OQYSr+DrfZ8aAFKoYg7dR7ftJ67PJ2Tr/rrmWzzNy F/8Mgu/TlR9ezKTZaEZ5ys9eroWlvI62uu+wL2YAxkvxudYNKNAEJs7gs UmwSSpVxB7xwgXZtczcJVBwqCP3ZWH89DA5oyp4vBXRRHolvWi5XR3zLu Tn+xVcBGKhyzi2lex2pot9jXnz6dN2CJyUKg6kwBlAxjcE71Wy+oo+Zss g==; X-CSE-ConnectionGUID: Pq7kOCohSpCpkHB2hKxVNA== X-CSE-MsgGUID: Hy63nk6xQpCG+oi3nHpsrg== X-IronPort-AV: E=McAfee;i="6800,10657,11833"; a="83734408" X-IronPort-AV: E=Sophos;i="6.25,141,1779174000"; d="scan'208";a="83734408" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2026 06:57:04 -0700 X-CSE-ConnectionGUID: 0C6QQ6HHThir9QaGMzF4PQ== X-CSE-MsgGUID: KfYUTV13TLC2fZOV8Dg7ew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,141,1779174000"; d="scan'208";a="249207935" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by fmviesa007.fm.intel.com with ESMTP; 01 Jul 2026 06:56:59 -0700 From: Chen Yu To: tony.luck@intel.com, reinette.chatre@intel.com Cc: x86@kernel.org, linux-kernel@vger.kernel.org, tglx@kernel.org, bp@alien8.de, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, fenghuay@nvidia.com, babu.moger@amd.com, anil.keshavamurthy@broadcom.com, chen.yu@linux.dev, Hongyu Ning , Chen Yu Subject: [PATCH v5 08/10] fs/resctrl: Do not invoke smp_processor_id() in preemptible context Date: Wed, 1 Jul 2026 21:47:04 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Tony Luck Currently, mon_evt::any_cpu is false for all events associated with RDT_RESOURCE_L3. The MMIO-based CMT will set any_cpu to true in a follow-up patch. This change will trigger a warning when calling smp_processor_id() inside __l3_mon_event_count(), because __l3_mon_event_count() may be invoked from arbitrary CPUs in task context. Since the calling context is preemptible here, smp_processor_id() will emit a debug warning. To prepare for MMIO-based CMT reads, skip the current CPU lookup when an event's any_cpu flag is set. Events with this flag do not require execution on a specific CPU. Signed-off-by: Tony Luck Tested-by: Hongyu Ning Signed-off-by: Chen Yu --- v4->v5: No change. --- fs/resctrl/monitor.c | 42 ++++++++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/fs/resctrl/monitor.c b/fs/resctrl/monitor.c index 0e6a389a16bf..6a7c86a72c51 100644 --- a/fs/resctrl/monitor.c +++ b/fs/resctrl/monitor.c @@ -417,9 +417,37 @@ static void mbm_cntr_free(struct rdt_l3_mon_domain *d, int cntr_id) memset(&d->cntr_cfg[cntr_id], 0, sizeof(*d->cntr_cfg)); } +/** + * cpu_on_correct_domain() - Check if current CPU is in the correct + * domain for the event. + * @rr: The rmid_read structure containing event and domain information. + * + * Context: Preemptible process context when @rr->evt->any_cpu is set. + * Non-migratable process context (via smp_call_on_cpu()) or + * non-preemptible context (via smp_call_function_any()) when + * the event must be read on a specific CPU. + * Return: true if the current CPU can read this event, false otherwise. + */ +static bool cpu_on_correct_domain(struct rmid_read *rr) +{ + int cpu; + + /* Any CPU is OK for this event */ + if (rr->evt->any_cpu) + return true; + + cpu = smp_processor_id(); + + /* Single domain. Must be on a CPU in that domain. */ + if (rr->hdr) + return cpumask_test_cpu(cpu, &rr->hdr->cpu_mask); + + /* Summing domains that share a cache, must be on a CPU for that cache. */ + return cpumask_test_cpu(cpu, &rr->ci->shared_cpu_map); +} + static int __l3_mon_event_count(struct rdtgroup *rdtgrp, struct rmid_read *rr) { - int cpu = smp_processor_id(); u32 closid = rdtgrp->closid; u32 rmid = rdtgrp->mon.rmid; struct rdt_l3_mon_domain *d; @@ -452,9 +480,6 @@ static int __l3_mon_event_count(struct rdtgroup *rdtgrp, struct rmid_read *rr) return 0; } - /* Reading a single domain, must be on a CPU in that domain. */ - if (!cpumask_test_cpu(cpu, &d->hdr.cpu_mask)) - return -EINVAL; if (rr->is_mbm_cntr) rr->err = resctrl_arch_cntr_read(rr->r, d, closid, rmid, cntr_id, rr->evt->evtid, &tval); @@ -472,7 +497,6 @@ static int __l3_mon_event_count(struct rdtgroup *rdtgrp, struct rmid_read *rr) static int __l3_mon_event_count_sum(struct rdtgroup *rdtgrp, struct rmid_read *rr) { - int cpu = smp_processor_id(); u32 closid = rdtgrp->closid; u32 rmid = rdtgrp->mon.rmid; struct rdt_l3_mon_domain *d; @@ -490,10 +514,6 @@ static int __l3_mon_event_count_sum(struct rdtgroup *rdtgrp, struct rmid_read *r return -EINVAL; } - /* Summing domains that share a cache, must be on a CPU for that cache. */ - if (!cpumask_test_cpu(cpu, &rr->ci->shared_cpu_map)) - return -EINVAL; - /* * Legacy files must report the sum of an event across all * domains that share the same L3 cache instance. @@ -524,7 +544,9 @@ static int __mon_event_count(struct rdtgroup *rdtgrp, struct rmid_read *rr) { switch (rr->r->rid) { case RDT_RESOURCE_L3: - WARN_ON_ONCE(rr->evt->any_cpu); + if (!cpu_on_correct_domain(rr)) + return -EINVAL; + if (rr->hdr) return __l3_mon_event_count(rdtgrp, rr); else -- 2.45.2