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Mon, 13 Oct 2025 22:43:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH3trdEiZsOPClRk6Dsifi/viN4KHN7PYNnvGAEG9JdzBt9jMbgdpd2Oj5WQlapWC0s77Wzcw== X-Received: by 2002:a17:90a:e7c7:b0:32d:601d:f718 with SMTP id 98e67ed59e1d1-33b51393502mr30831433a91.31.1760420632058; Mon, 13 Oct 2025 22:43:52 -0700 (PDT) Received: from [10.218.42.132] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b678df48a83sm11470944a12.31.2025.10.13.22.43.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Oct 2025 22:43:51 -0700 (PDT) Message-ID: Date: Tue, 14 Oct 2025 11:13:42 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/4] arm64: dts: qcom: Add PCIe 3 support for HAMOA-IOT-SOM platform To: Ziyue Zhang , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com References: <20250922075509.3288419-1-ziyue.zhang@oss.qualcomm.com> <20250922075509.3288419-4-ziyue.zhang@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20250922075509.3288419-4-ziyue.zhang@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=K88v3iWI c=1 sm=1 tr=0 ts=68ede319 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=kM70mR4GnouSU5tgWfoA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: MLK5oNIYfACTLrYtOMRSYjGqG0oFCazA X-Proofpoint-ORIG-GUID: MLK5oNIYfACTLrYtOMRSYjGqG0oFCazA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDEzMDAzNSBTYWx0ZWRfX9A2Vwcwfq7Et ES6iUHUirMnxFfBa0zwKnp4gMBuKUhAr3Q5PFCZPQykU5Le8z0R2xhV+FP6lQXY7xtqYVRNV/ih ca1o936P0pflUwnbnMv0g2RrIMs8IY0QW+NyE84IeJ3a/Jr7wnixpcBjkvEtGRDLVVAFr2jN9hE G972uVUtlEWODkiTO6Jzr/dmHLwAsxpBUhUHl+ZPQy86IU0Cyw794J5Yy3lTV9/ghT20CtR9wEc 1GutXndVKyCIyU3oF5it6kE7LHZ8UWaTlz/fZZ+BABplUno79zf9WMEoc7HOke6qBIvFzRseHJm K+fwaXGtWZpjSkVRA+gSGpBdljYJUUSHUwuAQU4D9eL5URGRtMHMHbqlEpsuMNWvfOrPdTciyiX MWbX6GvJfucRGLo9cAEkDiANmdpphQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-13_09,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1015 bulkscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510130035 On 9/22/2025 1:25 PM, Ziyue Zhang wrote: > Update the HAMOA-IOT-SOM device tree to enable PCIe 3 support. Add perst > wake and clkreq sideband signals and required regulators in PCIe3 > controller and PHY device tree node. > > Signed-off-by: Ziyue Zhang --- > arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 70 +++++++++++++++++++++ > 1 file changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi > index 0c8ae34c1f37..7486204a4a46 100644 > --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi > +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi > @@ -390,6 +390,53 @@ &gpu_zap_shader { > firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; > }; > > +&pm8550ve_8_gpios { > + pcie_x8_12v: pcie-12v-default-state { > + pins = "gpio8"; > + function = "normal"; > + output-enable; > + output-high; > + bias-pull-down; > + power-source = <0>; > + }; > +}; > + > +&pmc8380_3_gpios { > + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { > + pins = "gpio8"; > + function = "normal"; > + output-enable; > + output-high; > + bias-pull-down; > + power-source = <0>; > + }; > + > + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { > + pins = "gpio6"; > + function = "normal"; > + output-enable; > + output-high; > + bias-pull-down; > + power-source = <0>; > + }; > +}; Either squash patch 3/4 with 4/4 or move these pin configuration to patch 4/4. - Krishna Chaitanya. > + > +&pcie3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie3_default>; > + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; > + > + status = "okay"; > +}; > + > +&pcie3_phy { > + vdda-phy-supply = <&vreg_l3c_0p8>; > + vdda-pll-supply = <&vreg_l3e_1p2>; > + > + status = "okay"; > +}; > + > &pcie4 { > perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; > wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; > @@ -471,6 +518,29 @@ &tlmm { > gpio-reserved-ranges = <34 2>, /* TPM LP & INT */ > <44 4>; /* SPI (TPM) */ > > + pcie3_default: pcie3-default-state { > + clkreq-n-pins { > + pins = "gpio144"; > + function = "pcie3_clk"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + perst-n-pins { > + pins = "gpio143"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + wake-n-pins { > + pins = "gpio145"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + > pcie4_default: pcie4-default-state { > clkreq-n-pins { > pins = "gpio147";