From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9AA992F7477 for ; Thu, 20 Nov 2025 10:45:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763635516; cv=none; b=RxNryWN1sMjtuWvYYsRz9dJKIJC6l3m4TrKK/rxvOaU4vQeweMdLr8ImbmGoTg6aSKyE4YkYrSuXyw2qwNuXR52ALOPg+esp9EhnQgDrRBbJKwYI7HzeaZnKWnZm5ghDJ1sUIw3gokAZ7W6lu4PX2gF/PnaLaxXVf+KmZjMq6to= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763635516; c=relaxed/simple; bh=Qi7XfbvRY6B1lxLgBluvLNKZStaVmU1h1NVPeEtq/M8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=T5gB6oFOadoZvFBRktQkMOUzICQbmMFQEjtSiQw1Mf5xRBRIvQNhGb1PJZnSenSQMrKQ4VB/iZSc3SedD1gOUEfhRI6EPfb67oFPcbGBg9iVGrFPlqUgN8HJI/LWLothjNZM4Ju0avicvdiHYQpK20CVQ40kKEt2/rffiYBdNoA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CEF6F339; Thu, 20 Nov 2025 02:44:59 -0800 (PST) Received: from [10.1.197.1] (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DA9143F740; Thu, 20 Nov 2025 02:45:05 -0800 (PST) Message-ID: Date: Thu, 20 Nov 2025 10:45:04 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/3] coresight: tmc: refactor the tmc-etr mode setting to avoid race conditions To: Leo Yan Cc: Junhao He , james.clark@linaro.org, anshuman.khandual@arm.com, yeoreum.yun@arm.com, mike.leach@linaro.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linuxarm@huawei.com, jonathan.cameron@huawei.com References: <20251111122149.1981162-1-hejunhao3@h-partners.com> <20251111122149.1981162-3-hejunhao3@h-partners.com> <15868ecb-c1e7-4273-a2e2-5c10f2701c0b@arm.com> <20251119180447.GG8204@e132581.arm.com> Content-Language: en-US From: Suzuki K Poulose In-Reply-To: <20251119180447.GG8204@e132581.arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 19/11/2025 18:04, Leo Yan wrote: > On Thu, Nov 13, 2025 at 03:02:45PM +0000, Suzuki Kuruppassery Poulose wrote: >> Hi Junhao, >> >> While your patch fixes the problem it introduces imbalance in the >> way perf vs sysfs modes are handled. > > Previously, I suggested setting the mode in a unified way in > tmc_enable_etr_sink() [1]. After looking into the code again, it seems > that both my suggestion and this patch set the perf mode is too late. > > Maybe we need to set the sink's device mode once a session starts to use > it. So we should set the perf mode when allocating sink's buffer > (tmc_alloc_etr_buffer()), as this is the first callback invoked for a > perf session. Thats too early, in setup_aux(), when the event is not scheduled in. We don't know when that would be. > > As a result, we can keep to set the sysfs mode in > tmc_enable_etr_sink_sysfs(). > > A side topic is we need to refactor the tmc_etr_get_sysfs_buffer() > function, ideally this function is purely for allocating buffer without > any locking. We can defer to assign "drvdata->sysfs_buf" until > acquired spin lock in tmc_enable_etr_sink_sysfs(). Essetionally, we > can enable sink in one go rather than acquire-release lock for several > times. Patche welcome :-) Cheers Suzuki > > Thanks, > Leo > > [1] https://lore.kernel.org/linux-arm-kernel/20251020143718.GH281971@e132581.arm.com/