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From: Nicolas Dufresne To: "jackson.lee" , mchehab@kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, nas.chung@chipsnmedia.com Cc: lafley.kim@chipsnmedia.com, b-brnich@ti.com Date: Wed, 07 Feb 2024 13:00:06 -0500 In-Reply-To: <20240131013046.15687-3-jackson.lee@chipsnmedia.com> References: <20240131013046.15687-1-jackson.lee@chipsnmedia.com> <20240131013046.15687-3-jackson.lee@chipsnmedia.com> Autocrypt: addr=nicolas@ndufresne.ca; prefer-encrypt=mutual; keydata=mQGiBEUQN0MRBACQYceNSezSdMjx7sx6gwKkMghrrODgl3B0eXBTgNp6c431IfOOEsdvkoOh1kwoYcQgbg4MXw6beOltysX4e8fFWsiRkc2nvvRW9ir9kHDm49MkBLqaDjTqOkYKNMiurFW+gozpr/lUW15QqT6v68RYe0zRdtwGZqeLzX2LVuukGwCg4AISzswrrYHNV7vQLcbaUhPgIl0D+gILYT9TJgAEK4YHW+bFRcY+cgUFoLQqQayECMlctKoLOE69nIYOc/hDr9uih1wxrQ/yL0NJvQCohSPyoyLF9b2EuIGhQVp05XP7FzlTxhYvGO/DtO08ec85+bTfVBMV6eeY4MS3ZU+1z7ObD7Pf29YjyTehN2Dan6w1g2rBk5MoA/9nDocSlk4pbFpsYSFmVHsDiAOFje3+iY4ftVDKunKYWMhwRVBjAREOByBagmRau0cLEcElpf4hX5f978GoxSGIsiKoDAlXX+ICDOWC1/EXhEEmBR1gL0QJgiVviNyLfGJlZWnPjw6xhhmtHYWTDxBOP5peztyc2PqeKsLsLWzAr7RDTmljb2xhcyBEdWZyZXNuZSAoQi4gU2MuIEluZm9ybWF0aXF1ZSkgPG5pY29sYXMuZHVmcmVzbmVAZ21haWwuY29tPohgBBMRAgAgBQJFlCyOAhsDBgsJCAcDAgQVAggDBBYCAwECHgECF4AACgkQcVMCLawGqBwhLQCgzYlrLBj6KIAZ4gmsfjXD6ZtddT8AoIeGDicVq5WvMHNWign6ApQcZUihtElOaWNvbGFzIER1ZnJlc25lIChCLiBTYy4gSW5mb3JtYXRpcXVlKSA8bmljb2xhcy5kdWZyZXNuZUBjb2xsYWJvcmEuY28udWs+iGIEExECACIFAkuzca8CGwMGCwkIBwMCBhUIAgkKCwQWA gMBAh4BAheAAAoJEHFTAi2sBqgcQX8An2By6LDEeMxi4B9hUbpvRnzaaeNqA J9Rox8rfqHZnSErw9bCHiBwvwJZ77QxTmljb2xhcyBEdWZyZXNuZSA8bmljb2xhcy5kdWZyZXNuZUBjb2xsYWJvcmEuY29tPohiBBMRAgAiBQJNzZzPAhsDBgsJCAcDAgYVCAIJCgsEFgIDAQIeAQIXgAAKCRBxUwItrAaoHLlxAKCYAGf4JL7DYDLs/188CPMGuwLypwCfWKc9DorA9f5pyYlD5pQo6SgSoiC0J05pY29sYXMgRHVmcmVzbmUgPG5pY29sYXNAbmR1ZnJlc25lLmNhPohiBBMRAgAiBQJVwNwgAhsDBgsJCAcDAgYVCAIJCgsEFgIDAQIeAQIXgAAKCRBxUwItrAaoHCZ4AJ0QwU6/G4c7h9CkMBT9ZxGLX4KSnQCgq0P7CX7hv/M7HeyfMFZe8t3vAEW0RE5pY29sYXMgRHVmcmVzbmUgKEIuIFNjLiBJbmZvcm1hdGlxdWUpIDxuaWNvbGFzZEBibHVlc3RyZWFrdGVjaC5jb20+iGAEExECACAFAkZjGzoCGwMGCwkIBwMCBBUCCAMEFgIDAQIeAQIXgAAKCRBxUwItrAaoHBl7AJ0d2lrzshMmJaik/EaDEakzEwqgxQCg0JVZMZm9gRfEou1FvinuZxwf/mu0R05pY29sYXMgRHVmcmVzbmUgKEIgU2MuIEluZm9ybWF0aXF1ZSkgPG5pY29sYXMuZHVmcmVzbmVAdXNoZXJicm9va2UuY2E+iGAEExECACAFAkUQN0MCGwMGCwkIBwMCBBUCCAMEFgIDAQIeAQIXgAAKCRBxUwItrAaoHPTnAJ0WGgJJVspoctAvEcI00mtp5WAFGgCgr+E7ItOqZEHAs+xabBgknYZIFPW5Ag0ERRA3UhAIAJ0rxl2HsVg/nSOAUt7U/T/W+RKzVAlD9orCB0pRVvyWNxSr8MHcH mWCxykLuB34ouM4GuDVRKfGnqLzJRBfjs7Ax9K2FI3Odund9xpviLCt1jFC0K XL04RebrFT7xjDfocDaSLFvgxMVs/Jr2/ckKPId1oKvgYgt/o+MzUabKyFB8wIvq4GMtj3LoBKLCie2nCaSt7uVUt6q2t5bNWrd3lO6/mWn7YMc5Hsn33H9pS0+9szw6m3dG08eMKNueDlt72QxiYl2rhjzkT4ltKEkFgYBdyrtIj1UO6eX+YXb4E1rCMJrdjBSgqDPK1sWHC7gliy+izr+XTHuFwlfy8gBpsAAwUIAJJNus64gri4HAL632eqVpza83EphX1IuHzLi1LlMnQ9Tm7XKag46NhmJbOByMG33LwBsBdLjjHQSVkYZFWUifq+NWSFC/kqlb72vW8rBAv64+i3QdfxK9FWbweiRsPpvuHjJQuecbPDJpubLaxKbu2aqLCN5LuHXvdQr6KiXwabT+OJ9AJAqHG7q4IEzg4RNUVn9AS6L8bxqMSocjqpWNBCY2efCVd/c6k4Acv6jXu+wDAZEbWXK+71uaUHExhigBYBpiHGrobe32YlTVE/XEIzKKywhm/Hkn5YKWzumLte6xiD9JhKabmD7uqIvLt2twUpz4BdPzj0dvGlSmvFcaaISQQYEQIACQUCRRA3UgIbDAAKCRBxUwItrAaoHJLyAKDeS3AFowM3f1Y3OFU6XRCTKK2ZhwCfT/7P9WDjkkmiq5AfeOiwVlpuHtM= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.3 (3.50.3-1.fc39) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Jackson, Le mercredi 31 janvier 2024 =C3=A0 10:30 +0900, jackson.lee a =C3=A9crit=C2= =A0: > Indicates whether to generate SPS and PPS at every IDR. Setting it to 0 d= isables generating SPS and PPS at every IDR. > Setting it to one enables generating SPS and PPS at every IDR. >=20 > Signed-off-by: Jackson Lee > Signed-off-by: Nas Chung > --- > drivers/media/platform/chips-media/wave5/wave5-hw.c | 6 ++++-- > drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c | 7 +++++++ > drivers/media/platform/chips-media/wave5/wave5-vpuapi.h | 1 + > 3 files changed, 12 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/driver= s/media/platform/chips-media/wave5/wave5-hw.c > index f1e022fb148e..8ad7f3a28ae1 100644 > --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c > +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c > @@ -1602,11 +1602,13 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *i= nst) > if (inst->std =3D=3D W_AVC_ENC) > vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp= | > ((p_param->intra_period & 0x7ff) << 6) | > - ((p_param->avc_idr_period & 0x7ff) << 17)); > + ((p_param->avc_idr_period & 0x7ff) << 17) | > + (p_param->forced_idr_header_enable << 28)); I can spot evident hard-coding of mask and bit shifts in here. In order to continuously improve this driver code, I would like to see this (and the following) magic number being defined with well named macros as a preparati= on patch to this feature change. regards, Nicolas > else if (inst->std =3D=3D W_HEVC_ENC) > vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, > p_param->decoding_refresh_type | (p_param->intra_qp << 3) | > - (p_param->intra_period << 16)); > + (p_param->forced_idr_header_enable << 9) | > + (p_param->intra_period << 16)); > =20 > reg_val =3D (p_param->rdo_skip << 2) | > (p_param->lambda_scaling_enable << 3) | > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/d= rivers/media/platform/chips-media/wave5/wave5-vpu-enc.c > index 0cb5bfb67258..761775216cd4 100644 > --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c > @@ -1125,6 +1125,9 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *c= trl) > case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: > inst->enc_param.entropy_coding_mode =3D ctrl->val; > break; > + case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: > + inst->enc_param.forced_idr_header_enable =3D ctrl->val; > + break; > case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT: > break; > default: > @@ -1292,6 +1295,7 @@ static void wave5_set_enc_openparam(struct enc_open= _param *open_param, > else > open_param->wave_param.intra_refresh_arg =3D num_ctu_row; > } > + open_param->wave_param.forced_idr_header_enable =3D input.forced_idr_he= ader_enable; > } > =20 > static int initialize_sequence(struct vpu_instance *inst) > @@ -1775,6 +1779,9 @@ static int wave5_vpu_open_enc(struct file *filp) > 0, 1, 1, 0); > v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR, > + 0, 1, 1, 0); > =20 > if (v4l2_ctrl_hdl->error) { > ret =3D -ENODEV; > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/dr= ivers/media/platform/chips-media/wave5/wave5-vpuapi.h > index 352f6e904e50..3ad6118550ac 100644 > --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h > @@ -566,6 +566,7 @@ struct enc_wave_param { > u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP= */ > u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 tran= sform */ > u32 mb_level_rc_enable: 1; /* enable MB-level rate control */ > + u32 forced_idr_header_enable: 1; /* enable header encoding before IDR f= rame */ > }; > =20 > struct enc_open_param {