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[149.14.88.27]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74af557439csm11016401b3a.80.2025.07.01.00.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 00:55:05 -0700 (PDT) Message-ID: Subject: Re: [RESEND PATCH v9 1/4] PCI: rockchip: Use standard PCIe defines From: Philipp Stanner To: Geraldo Nascimento , linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?UTF-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Rick wertenbroek , Neil Armstrong , Valmantas Paliksa , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Date: Tue, 01 Jul 2025 09:54:51 +0200 In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-2.fc40) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2025-06-30 at 19:24 -0300, Geraldo Nascimento wrote: > Current code uses custom-defined register offsets and bitfields for > standard PCIe registers. Change to using standard PCIe defines. Since > we are now using standard PCIe defines, drop unused custom-defined > ones, > which are now referenced from offset at added Capabilities Register. This could be phrased a bit more cleanly. At least I don't get exactly what "from offset" means. You mean you replace the unused custom ones? But if they're unused, why are they even being replaced? >=20 > Suggested-By: Bjorn Helgaas s/By/by P. > Signed-off-by: Geraldo Nascimento > --- > =C2=A0drivers/pci/controller/pcie-rockchip-ep.c=C2=A0=C2=A0 |=C2=A0 4 +- > =C2=A0drivers/pci/controller/pcie-rockchip-host.c | 44 ++++++++++--------= - > -- > =C2=A0drivers/pci/controller/pcie-rockchip.h=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 | 12 +----- > =C2=A03 files changed, 25 insertions(+), 35 deletions(-) >=20 > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c > b/drivers/pci/controller/pcie-rockchip-ep.c > index 55416b8311dd..300cd85fa035 100644 > --- a/drivers/pci/controller/pcie-rockchip-ep.c > +++ b/drivers/pci/controller/pcie-rockchip-ep.c > @@ -518,9 +518,9 @@ static void rockchip_pcie_ep_retrain_link(struct > rockchip_pcie *rockchip) > =C2=A0{ > =C2=A0 u32 status; > =C2=A0 > - status =3D rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_LCS); > + status =3D rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + > PCI_EXP_LNKCTL); > =C2=A0 status |=3D PCI_EXP_LNKCTL_RL; > - rockchip_pcie_write(rockchip, status, PCIE_EP_CONFIG_LCS); > + rockchip_pcie_write(rockchip, status, PCIE_EP_CONFIG_BASE + > PCI_EXP_LNKCTL); > =C2=A0} > =C2=A0 > =C2=A0static bool rockchip_pcie_ep_link_up(struct rockchip_pcie *rockchip= ) > diff --git a/drivers/pci/controller/pcie-rockchip-host.c > b/drivers/pci/controller/pcie-rockchip-host.c > index b9e7a8710cf0..65653218b9ab 100644 > --- a/drivers/pci/controller/pcie-rockchip-host.c > +++ b/drivers/pci/controller/pcie-rockchip-host.c > @@ -40,18 +40,18 @@ static void rockchip_pcie_enable_bw_int(struct > rockchip_pcie *rockchip) > =C2=A0{ > =C2=A0 u32 status; > =C2=A0 > - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); > + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + > PCI_EXP_LNKCTL); > =C2=A0 status |=3D (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE); > - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); > + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + > PCI_EXP_LNKCTL); > =C2=A0} > =C2=A0 > =C2=A0static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip= ) > =C2=A0{ > =C2=A0 u32 status; > =C2=A0 > - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); > + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + > PCI_EXP_LNKCTL); > =C2=A0 status |=3D (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16; > - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); > + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + > PCI_EXP_LNKCTL); > =C2=A0} > =C2=A0 > =C2=A0static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie > *rockchip) > @@ -269,7 +269,7 @@ static void rockchip_pcie_set_power_limit(struct > rockchip_pcie *rockchip) > =C2=A0 scale =3D 3; /* 0.001x */ > =C2=A0 curr =3D curr / 1000; /* convert to mA */ > =C2=A0 power =3D (curr * 3300) / 1000; /* milliwatt */ > - while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) { > + while (power > FIELD_MAX(PCI_EXP_DEVCAP_PWR_VAL)) { > =C2=A0 if (!scale) { > =C2=A0 dev_warn(rockchip->dev, "invalid power > supply\n"); > =C2=A0 return; > @@ -278,10 +278,10 @@ static void > rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip) > =C2=A0 power =3D power / 10; > =C2=A0 } > =C2=A0 > - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR); > - status |=3D (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) | > - =C2=A0 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT); > - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR); > + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + > PCI_EXP_DEVCAP); > + status |=3D FIELD_PREP(PCI_EXP_DEVCAP_PWR_VAL, power); > + status |=3D FIELD_PREP(PCI_EXP_DEVCAP_PWR_SCL, scale); > + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + > PCI_EXP_DEVCAP); > =C2=A0} > =C2=A0 > =C2=A0/** > @@ -309,14 +309,14 @@ static int rockchip_pcie_host_init_port(struct > rockchip_pcie *rockchip) > =C2=A0 rockchip_pcie_set_power_limit(rockchip); > =C2=A0 > =C2=A0 /* Set RC's clock architecture as common clock */ > - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); > + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + > PCI_EXP_LNKCTL); > =C2=A0 status |=3D PCI_EXP_LNKSTA_SLC << 16; > - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); > + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + > PCI_EXP_LNKCTL); > =C2=A0 > =C2=A0 /* Set RC's RCB to 128 */ > - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); > + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + > PCI_EXP_LNKCTL); > =C2=A0 status |=3D PCI_EXP_LNKCTL_RCB; > - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); > + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + > PCI_EXP_LNKCTL); > =C2=A0 > =C2=A0 /* Enable Gen1 training */ > =C2=A0 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, > @@ -341,9 +341,9 @@ static int rockchip_pcie_host_init_port(struct > rockchip_pcie *rockchip) > =C2=A0 * Enable retrain for gen2. This should be > configured only after > =C2=A0 * gen1 finished. > =C2=A0 */ > - status =3D rockchip_pcie_read(rockchip, > PCIE_RC_CONFIG_LCS); > + status =3D rockchip_pcie_read(rockchip, > PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); > =C2=A0 status |=3D PCI_EXP_LNKCTL_RL; > - rockchip_pcie_write(rockchip, status, > PCIE_RC_CONFIG_LCS); > + rockchip_pcie_write(rockchip, status, > PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); > =C2=A0 > =C2=A0 err =3D readl_poll_timeout(rockchip->apb_base + > PCIE_CORE_CTRL, > =C2=A0 status, > PCIE_LINK_IS_GEN2(status), 20, > @@ -380,15 +380,15 @@ static int rockchip_pcie_host_init_port(struct > rockchip_pcie *rockchip) > =C2=A0 > =C2=A0 /* Clear L0s from RC's link cap */ > =C2=A0 if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) { > - status =3D rockchip_pcie_read(rockchip, > PCIE_RC_CONFIG_LINK_CAP); > - status &=3D ~PCIE_RC_CONFIG_LINK_CAP_L0S; > - rockchip_pcie_write(rockchip, status, > PCIE_RC_CONFIG_LINK_CAP); > + status =3D rockchip_pcie_read(rockchip, > PCIE_RC_CONFIG_CR + PCI_EXP_LNKCAP); > + status &=3D ~PCI_EXP_LNKCAP_ASPM_L0S; > + rockchip_pcie_write(rockchip, status, > PCIE_RC_CONFIG_CR + PCI_EXP_LNKCAP); > =C2=A0 } > =C2=A0 > - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR); > - status &=3D ~PCIE_RC_CONFIG_DCSR_MPS_MASK; > - status |=3D PCIE_RC_CONFIG_DCSR_MPS_256; > - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR); > + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + > PCI_EXP_DEVCTL); > + status &=3D ~PCI_EXP_DEVCTL_PAYLOAD; > + status |=3D PCI_EXP_DEVCTL_PAYLOAD_256B; > + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + > PCI_EXP_DEVCTL); > =C2=A0 > =C2=A0 return 0; > =C2=A0err_power_off_phy: > diff --git a/drivers/pci/controller/pcie-rockchip.h > b/drivers/pci/controller/pcie-rockchip.h > index 5864a20323f2..f5cbf3c9d2d9 100644 > --- a/drivers/pci/controller/pcie-rockchip.h > +++ b/drivers/pci/controller/pcie-rockchip.h > @@ -155,17 +155,7 @@ > =C2=A0#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) > =C2=A0#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) > =C2=A0#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) > -#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) > -#define=C2=A0=C2=A0 PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 > -#define=C2=A0=C2=A0 PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff > -#define=C2=A0=C2=A0 PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 > -#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) > -#define=C2=A0=C2=A0 PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5) > -#define=C2=A0=C2=A0 PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5) > -#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE > + 0xcc) > -#define=C2=A0=C2=A0 PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) > -#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) > -#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) > +#define PCIE_RC_CONFIG_CR (PCIE_RC_CONFIG_BASE + 0xc0) > =C2=A0#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + > 0x90c) > =C2=A0#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + > 0x274) > =C2=A0#define=C2=A0=C2=A0 PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20= )