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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-127899dfc47sm21089438c88.6.2026.03.03.16.15.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Mar 2026 16:15:49 -0800 (PST) Message-ID: Date: Tue, 3 Mar 2026 16:15:48 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema To: Bryan O'Donoghue , Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260226-x1e-csi2-phy-v3-0-11e608759410@linaro.org> <20260226-x1e-csi2-phy-v3-1-11e608759410@linaro.org> <4pFL6wOeTKUt-Zq4YbjqJdacMgUIPSYJD-4-5DcIMEZ1sM7JsNFYcSv1bd7ZRVOklTsmkEfxM2b6tTflmiECNQ==@protonmail.internalid> <03b44922-72d5-465b-96e1-97a19655e97d@kernel.org> <4440a3a8-7281-4bea-bb84-7a9d19ef7ce9@oss.qualcomm.com> <2a1155bd-7dc5-4ed8-b1eb-ddfa483c75ca@oss.qualcomm.com> <4fea7117-ebd3-4279-9973-3ac4f2a78835@linaro.org> <8e7c2036-74de-4f21-8269-8e2b24323753@oss.qualcomm.com> <39828202-9f48-44f9-9f28-574f141e2ee9@linaro.org> Content-Language: en-US From: Vijay Kumar Tumati In-Reply-To: <39828202-9f48-44f9-9f28-574f141e2ee9@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: BXe7WjYDPLirg-3FhmSphsKjmDCorMAC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA0MDAwMCBTYWx0ZWRfX7Bka873g9DtF n28irjndKybIh39n+dVEMAApUYkObv/aA3zlEprbjaRrkR+ZZl7FgomN6AlSnqhrRfFSc/G+t/U rbMYf93gRIzDDTVn7h+GemfcHaEHBK1HUbXmlpEKpkJTpYhGqapq2/CFs8CjAwUeaYJ+DhS00CV UYGnrflNtxjMv8nNzLjUynG7RjHI5LU6W5u++6YMsuqe3B4BT4Kbrzs9S+XNNcOR7ESjBCzepK0 eRq6Kh6XjykVRMWy4b/PfglglVlv59JrhZchkp8Mkz3T9NzRX4P+x4pwQsRtCVd9/XsJRxakNCj sAhkTGOk8dGUjT6cqpc9dhN14tpH6pyWlbUGhlikjXH2PJSnGVGdtzynH8mYnd0iVQ6nSc52A9v IrczfIF1FJOmhbqgTuTQQ/IxA6Ann7wUDjZqF0j5HMNB2RnFWnHYRl2rTJlmTiVnuD0V54Ly4cm 05A7plDp8XiQBhP6o1Q== X-Authority-Analysis: v=2.4 cv=TtHrRTXh c=1 sm=1 tr=0 ts=69a779b6 cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=CgQL4hy3QgFxKJLL_JIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-GUID: BXe7WjYDPLirg-3FhmSphsKjmDCorMAC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-03_03,2026-03-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 phishscore=0 suspectscore=0 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603040000 On 3/3/2026 4:02 PM, Bryan O'Donoghue wrote: > On 03/03/2026 23:50, Vijay Kumar Tumati wrote: >> Sure, I was just giving an example. I haven't looked a lot into the >> IPCAT / clock corners of this target particularly. Someone needs to >> check the clock plan, > > I mean, feel free. > > understand which PHYs require which power domains >> and add that in the following OPP table and as for scaling you can use >> the same RPMH levels for all those power domains. Btw, if you had >> defined the below OPP table for TOP GDSC, I think that is wrong. It >> only has two perf states (on and off) and doesn't need OPP scaling. If >> you look at the Iris driver, they link only the mxc and mmcx power >> domains to the OPP table using 'PD_FLAG_REQUIRED_OPP, not the GDSCs. >>> >>> +    csiphy_opp_table: opp-table-csiphy { >>> +        compatible = "operating-points-v2"; >>> + >>> +        opp-300000000 { >>> +            opp-hz = /bits/ 64 <300000000>; >>> +            required-opps = <&rpmhpd_opp_low_svs_d1>; >>> +        }; >>> + >>> +        opp-400000000 { >>> +            opp-hz = /bits/ 64 <400000000>; >>> +            required-opps = <&rpmhpd_opp_low_svs>; >>> +        }; >>> + >>> +        opp-480000000 { >>> +            opp-hz = /bits/ 64 <480000000>; >>> +            required-opps = <&rpmhpd_opp_low_svs>; >>> +        }; >>> +    }; >>> >>> --- >>> bod > > Yes, we should scale the MX*, that's incorrect. > > csiphy_mxc_opp_table: opp-table-csiphy-mxc { >     compatible = "operating-points-v2"; > >     opp-300000000 { >         opp-hz = /bits/ 64 <300000000>; >         required-opps = <&rpmhpd_opp_low_svs_d1>, >                         <&rpmhpd_opp_low_svs_d1>; >     }; > >     opp-400000000 { >         opp-hz = /bits/ 64 <400000000>; >         required-opps = <&rpmhpd_opp_low_svs>, >                         <&rpmhpd_opp_low_svs>; >     }; > >     opp-480000000 { >         opp-hz = /bits/ 64 <480000000>; >         required-opps = <&rpmhpd_opp_low_svs>, >                         <&rpmhpd_opp_low_svs>; >     }; > }; > > csiphy_mxa_opp_table: opp-table-csiphy-mxa { >     compatible = "operating-points-v2"; > >     opp-300000000 { >         opp-hz = /bits/ 64 <300000000>; >         required-opps = <&rpmhpd_opp_low_svs_d1>, >                         <&rpmhpd_opp_low_svs_d1>; >     }; > >     opp-400000000 { >         opp-hz = /bits/ 64 <400000000>; >         required-opps = <&rpmhpd_opp_low_svs>, >                         <&rpmhpd_opp_low_svs>; >     }; > >     opp-480000000 { >         opp-hz = /bits/ 64 <480000000>; >         required-opps = <&rpmhpd_opp_low_svs>, >                         <&rpmhpd_opp_low_svs>; >     }; > }; > > csiphy0: phy@ace4000 { >     power-domains = <&rpmhpd RPMHPD_MXC>, >                     <&rpmhpd RPMHPD_MMCX>; >     operating-points-v2 = <&csiphy_mxc_opp_table>; >     ... > }; > > csiphy4: phy@acec000 { >     power-domains = <&rpmhpd RPMHPD_MXA>, >                     <&rpmhpd RPMHPD_MMCX>; >     operating-points-v2 = <&csiphy_mxa_opp_table>; >     ... > }; > > --- > bod Yes, something like this based on this target architecture. A couple things though. You will still need to have the GDSC as a power domain and attach to it, just skip that from registering with the OPP framework . As I mentioned, if the RCG, 'cam_cc_cphy_rx_clk_src' depends on MXA (actually, I just checked for X1E80100 and it seems to require all three), the children of those (all CSIPHY clocks) indirectly depend on all three power domains. Additionally, This is the RCG for CSID and CSID Lite RX clocks as well but we can deal with those when we refactor the CSID nodes. Thanks, Vijay.