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[2001:1c00:c0c:fe00:6c10:fbf3:14c4:884c]) by smtp.gmail.com with ESMTPSA id k23sm8760275ejs.100.2020.11.09.05.50.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Nov 2020 05:50:01 -0800 (PST) Subject: Re: [PATCH v3 1/4] pinctrl: amd: fix incorrect way to disable debounce filter To: Coiby Xu , Linus Walleij Cc: Andy Shevchenko , linux-gpio@vger.kernel.org, open list References: <20201105231912.69527-1-coiby.xu@gmail.com> <20201105231912.69527-2-coiby.xu@gmail.com> From: Hans de Goede Message-ID: Date: Mon, 9 Nov 2020 14:50:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.3.1 MIME-Version: 1.0 In-Reply-To: <20201105231912.69527-2-coiby.xu@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 11/6/20 12:19 AM, Coiby Xu wrote: > The correct way to disable debounce filter is to clear bit 5 and 6 > of the register. > > Cc: Hans de Goede > Link: https://lore.kernel.org/linux-gpio/df2c008b-e7b5-4fdd-42ea-4d1c62b52139@redhat.com/ > Signed-off-by: Coiby Xu Thanks, patch looks good to me: Reviewed-by: Hans de Goede Regards, Hans > --- > drivers/pinctrl/pinctrl-amd.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c > index 9a760f5cd7ed..d6b2b4bd337c 100644 > --- a/drivers/pinctrl/pinctrl-amd.c > +++ b/drivers/pinctrl/pinctrl-amd.c > @@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, > pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); > pin_reg |= BIT(DB_TMR_LARGE_OFF); > } else { > - pin_reg &= ~DB_CNTRl_MASK; > + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); > ret = -EINVAL; > } > } else { > pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); > pin_reg &= ~BIT(DB_TMR_LARGE_OFF); > pin_reg &= ~DB_TMR_OUT_MASK; > - pin_reg &= ~DB_CNTRl_MASK; > + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); > } > writel(pin_reg, gpio_dev->base + offset * 4); > raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); >