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[165.204.72.6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36bbd01ee30sm1501150f8f.50.2024.08.02.02.39.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 02 Aug 2024 02:39:37 -0700 (PDT) Message-ID: Date: Fri, 2 Aug 2024 11:39:36 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/amdgpu: add dce6 drm_panic support To: Lu Yao , alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, srinivasan.shanmugam@amd.com, sunil.khatri@amd.com Cc: airlied@gmail.com, daniel@ffwll.ch, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20240802071752.116541-1-yaolu@kylinos.cn> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <20240802071752.116541-1-yaolu@kylinos.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Am 02.08.24 um 09:17 schrieb Lu Yao: > Add support for the drm_panic module, which displays a pretty user > friendly message on the screen when a Linux kernel panic occurs. > > Signed-off-by: Lu Yao > --- > The patch can work properly on the TTY, but after start X, drawn > image is messy, it looks like the data isn't linearly arranged. > However at this time 'fb->modifier' is 'DRM_FORMAT_MOD_LINEAR'. > > Another difference I found is: > For TTY, the amdgpu_bo is created with flag > 'AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED|AMDGPU_GEM_CREATE_CPU_GTT_USWC| > AMDGPU_GEM_CREATE_VRAM_CLEARED|AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS'. > For X, the amdgpu_bo is created with flag > 'AMDGPU_GEM_CREATE_NO_CPU_ACCESS|AMDGPU_GEM_CREATE_CPU_GTT_USWC' > I try to use same flag for X, it looks like no difference. > > Can someone provide some insight into this problem or where I am going > wrong. Thanks a lot. > > Test environment: X86 arch + v6.6 kernel + R7340. > --- > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 32 +++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c > index 05c0df97f01d..12c3801c264a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c > @@ -28,6 +28,8 @@ > #include > #include > #include > +#include > +#include "../../drm_internal.h" Well that this file is named "internal" and not in a common include directory is a strong indicator that you should absolutely *not* include it in a driver. > > #include "amdgpu.h" > #include "amdgpu_pm.h" > @@ -2600,6 +2602,35 @@ static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { > .get_scanout_position = amdgpu_crtc_get_scanout_position, > }; > > +static int dce_v6_0_drm_primary_plane_get_scanout_buffer(struct drm_plane *plane, > + struct drm_scanout_buffer *sb) > +{ > + struct drm_framebuffer *fb; > + struct drm_gem_object *obj; > + struct amdgpu_bo *abo; > + int ret = 0; > + > + if (!plane->fb || plane->fb->modifier != DRM_FORMAT_MOD_LINEAR) > + return -ENODEV; > + > + fb = plane->fb; > + sb->width = fb->width; > + sb->height = fb->height; > + sb->format = fb->format; > + sb->pitch[0] = fb->pitches[0]; > + > + obj = fb->obj[0]; > + abo = gem_to_amdgpu_bo(obj); > + if (!abo || abo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) > + return -EINVAL; > + > + return drm_gem_vmap(obj, &sb->map[0]); Yeah that will almost always not work. Most display buffers are tilled and not CPU accessible. Regards, Christian. > +} > + > +static const struct drm_plane_helper_funcs dce_v6_0_drm_primary_plane_helper_funcs = { > + .get_scanout_buffer = dce_v6_0_drm_primary_plane_get_scanout_buffer > +}; > + > static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) > { > struct amdgpu_crtc *amdgpu_crtc; > @@ -2627,6 +2658,7 @@ static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) > amdgpu_crtc->encoder = NULL; > amdgpu_crtc->connector = NULL; > drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); > + drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs); > > return 0; > }