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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b291d0fdd6sm2868216e87.0.2026.07.21.04.30.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jul 2026 04:30:02 -0700 (PDT) Message-ID: Date: Tue, 21 Jul 2026 14:30:01 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v13 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver To: Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260720-x1e-csi2-phy-v13-0-160c31958863@linaro.org> <20260720-x1e-csi2-phy-v13-2-160c31958863@linaro.org> From: Vladimir Zapolskiy In-Reply-To: <20260720-x1e-csi2-phy-v13-2-160c31958863@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/20/26 04:11, Bryan O'Donoghue wrote: > Add a new MIPI CSI2 driver in DPHY mode initially. The entire set of > existing CAMSS CSI PHY init sequences are imported in order to save time > and effort in later patches. > > The following devices are supported in this drop: > "qcom,x1e80100-csi2-phy" > > In-line with other PHY drivers the process node is included in the name. > Data-lane and clock lane positioning and polarity selection via newly > amended struct phy_configure_opts_mipi_dphy{} is supported. > > The Qualcomm 3PH class of PHYs can do both DPHY and CPHY mode. For now only > DPHY is supported. > > In porting some of the logic over from camss-csiphy*.c to here its also > possible to rationalise some of the code. > > In particular use of regulator_bulk and clk_bulk as well as dropping the > seemingly useless and unused interrupt handler. > > The PHY sequences and a lot of the logic that goes with them are well > proven in CAMSS and mature so the main thing to watch out for here is how > to get the right sequencing of regulators, clocks and register-writes. > > The register init sequence table is imported verbatim from the existing > CAMSS csiphy driver. A follow-up series will rework the table to extract > the repetitive per-lane pattern into a loop. > > Signed-off-by: Bryan O'Donoghue > --- > diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h > new file mode 100644 > index 0000000000000..7e55ae0073704 > --- /dev/null > +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h > @@ -0,0 +1,97 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * > + * Qualcomm MIPI CSI2 CPHY/DPHY driver > + * > + * Copyright (C) 2025 Linaro Ltd. > + */ > +#ifndef __PHY_QCOM_MIPI_CSI2_H__ > +#define __PHY_QCOM_MIPI_CSI2_H__ > + > +#include > + > +#define CSI2_MAX_DATA_LANES 4 > +#define CSI2_DEFAULT_CLK_LANE 7 There is no 7 lanes on CSIPHY, this value is bogus, also it was reported previously. The 'data-lanes' handling is broken in this version of the driver, since it does not follow the description from included video-interfaces.yaml. > + > +struct mipi_csi2phy_lane { > + u8 pos; > + u8 pol; > +}; > + > +struct mipi_csi2phy_lanes_cfg { > + struct mipi_csi2phy_lane data[CSI2_MAX_DATA_LANES]; > + struct mipi_csi2phy_lane clk; > +}; > + > +struct mipi_csi2phy_stream_cfg { > + s64 link_freq; > + u8 num_data_lanes; > + struct mipi_csi2phy_lanes_cfg lane_cfg; > +}; > + > +struct mipi_csi2phy_device; > + > +struct mipi_csi2phy_hw_ops { > + void (*hw_version_read)(struct mipi_csi2phy_device *csi2phy_dev); > + void (*reset)(struct mipi_csi2phy_device *csi2phy_dev); > + int (*lanes_enable)(struct mipi_csi2phy_device *csi2phy_dev, > + struct mipi_csi2phy_stream_cfg *cfg); > + void (*lanes_disable)(struct mipi_csi2phy_device *csi2phy_dev, > + struct mipi_csi2phy_stream_cfg *cfg); > +}; > + > +struct mipi_csi2phy_lane_regs { > + const s32 reg_addr; > + const s32 reg_data; > + const u32 delay_us; > + const u32 param_type; > +}; > + > +struct mipi_csi2phy_device_regs { > + const struct mipi_csi2phy_lane_regs *init_seq; > + const int lane_array_size; > + const u32 common_regs_offset; > +}; > + > +struct mipi_csi2_genpd { > + const char *name; > + bool scaled; > +}; > + > +struct mipi_csi2phy_soc_cfg { > + const struct mipi_csi2phy_hw_ops *ops; > + const struct mipi_csi2phy_device_regs reg_info; > + > + const char ** const supply_names; > + const unsigned int num_supplies; > + > + const char ** const clk_names; > + const unsigned int num_clk; > + > + const struct mipi_csi2_genpd *genpds; > + const unsigned int num_genpds; > +}; > + > +struct mipi_csi2phy_device { > + struct device *dev; > + u8 phy_mode; > + > + struct phy *phy; > + void __iomem *base; > + > + struct clk_bulk_data *clks; > + struct clk *timer_clk; > + u32 timer_clk_rate; > + > + struct regulator_bulk_data *supplies; > + struct dev_pm_domain_list *pd_list; > + > + const struct mipi_csi2phy_soc_cfg *soc_cfg; > + struct mipi_csi2phy_stream_cfg stream_cfg; > + > + u32 hw_version; > +}; > + > +extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e; > + > +#endif /* __PHY_QCOM_MIPI_CSI2_H__ */ > -- Best wishes, Vladimir