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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000397B4.mail.protection.outlook.com (10.167.248.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7828.19 via Frontend Transport; Tue, 6 Aug 2024 22:02:30 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 6 Aug 2024 17:02:29 -0500 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 11/22] x86/resctrl: Remove MSR reading of event configuration value Date: Tue, 6 Aug 2024 17:00:48 -0500 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B4:EE_|PH8PR12MB7135:EE_ X-MS-Office365-Filtering-Correlation-Id: 1dba7810-fc8d-418f-9434-08dcb66377d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 22:02:30.7595 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1dba7810-fc8d-418f-9434-08dcb66377d9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7135 The event configuration is domain specific and initialized during domain initialization. The values is stored in rdt_hw_mon_domain. It is not required to read the configuration register every time user asks for it. Use the value stored in rdt_hw_mon_domain instead. Introduce resctrl_arch_event_config_get() and resctrl_arch_event_config_set() to get/set architecture domain specific mbm_total_cfg/mbm_local_cfg values. Also, remove unused config value definitions. Signed-off-by: Babu Moger --- v6: Fixed inconstancy with types. Made all the types to u32 for config value. Removed few rdt_last_cmd_puts as it is not necessary. Removed unused config value definitions. Few more updates to commit message. v5: Introduced resctrl_arch_event_config_get and resctrl_arch_event_config_get() based on our discussion. https://lore.kernel.org/lkml/68e861f9-245d-4496-a72e-46fc57d19c62@amd.com/ v4: New patch. --- arch/x86/kernel/cpu/resctrl/internal.h | 21 ----- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 104 ++++++++++++++----------- include/linux/resctrl.h | 4 + 3 files changed, 64 insertions(+), 65 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index 4d8cc36a8d79..1021227d8c7e 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -32,27 +32,6 @@ */ #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE) -/* Reads to Local DRAM Memory */ -#define READS_TO_LOCAL_MEM BIT(0) - -/* Reads to Remote DRAM Memory */ -#define READS_TO_REMOTE_MEM BIT(1) - -/* Non-Temporal Writes to Local Memory */ -#define NON_TEMP_WRITE_TO_LOCAL_MEM BIT(2) - -/* Non-Temporal Writes to Remote Memory */ -#define NON_TEMP_WRITE_TO_REMOTE_MEM BIT(3) - -/* Reads to Local Memory the system identifies as "Slow Memory" */ -#define READS_TO_LOCAL_S_MEM BIT(4) - -/* Reads to Remote Memory the system identifies as "Slow Memory" */ -#define READS_TO_REMOTE_S_MEM BIT(5) - -/* Dirty Victims to All Types of Memory */ -#define DIRTY_VICTIMS_TO_ALL_MEM BIT(6) - /* Max event bits supported */ #define MAX_EVT_CONFIG_BITS GENMASK(6, 0) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 02afd3442876..0047b4eb0ff5 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1605,10 +1605,57 @@ static int rdtgroup_size_show(struct kernfs_open_file *of, } struct mon_config_info { + struct rdt_mon_domain *d; u32 evtid; u32 mon_config; }; +u32 resctrl_arch_event_config_get(struct rdt_mon_domain *d, + enum resctrl_event_id eventid) +{ + struct rdt_hw_mon_domain *hw_dom = resctrl_to_arch_mon_dom(d); + + switch (eventid) { + case QOS_L3_OCCUP_EVENT_ID: + break; + case QOS_L3_MBM_TOTAL_EVENT_ID: + return hw_dom->mbm_total_cfg; + case QOS_L3_MBM_LOCAL_EVENT_ID: + return hw_dom->mbm_local_cfg; + } + + /* Never expect to get here */ + WARN_ON_ONCE(1); + + return INVALID_CONFIG_VALUE; +} + +void resctrl_arch_event_config_set(void *info) +{ + struct mon_config_info *mon_info = info; + struct rdt_hw_mon_domain *hw_dom; + unsigned int index; + + index = mon_event_config_index_get(mon_info->evtid); + if (index == INVALID_CONFIG_INDEX) + return; + + wrmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, 0); + + hw_dom = resctrl_to_arch_mon_dom(mon_info->d); + + switch (mon_info->evtid) { + case QOS_L3_OCCUP_EVENT_ID: + break; + case QOS_L3_MBM_TOTAL_EVENT_ID: + hw_dom->mbm_total_cfg = mon_info->mon_config; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + hw_dom->mbm_local_cfg = mon_info->mon_config; + break; + } +} + /** * mon_event_config_index_get - get the hardware index for the * configurable event @@ -1631,33 +1678,11 @@ unsigned int mon_event_config_index_get(u32 evtid) } } -static void mon_event_config_read(void *info) -{ - struct mon_config_info *mon_info = info; - unsigned int index; - u64 msrval; - - index = mon_event_config_index_get(mon_info->evtid); - if (index == INVALID_CONFIG_INDEX) { - pr_warn_once("Invalid event id %d\n", mon_info->evtid); - return; - } - rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval); - - /* Report only the valid event configuration bits */ - mon_info->mon_config = msrval & MAX_EVT_CONFIG_BITS; -} - -static void mondata_config_read(struct rdt_mon_domain *d, struct mon_config_info *mon_info) -{ - smp_call_function_any(&d->hdr.cpu_mask, mon_event_config_read, mon_info, 1); -} - static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32 evtid) { - struct mon_config_info mon_info = {0}; struct rdt_mon_domain *dom; bool sep = false; + u32 val; cpus_read_lock(); mutex_lock(&rdtgroup_mutex); @@ -1666,11 +1691,11 @@ static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32 evtid if (sep) seq_puts(s, ";"); - memset(&mon_info, 0, sizeof(struct mon_config_info)); - mon_info.evtid = evtid; - mondata_config_read(dom, &mon_info); + val = resctrl_arch_event_config_get(dom, evtid); + if (val == INVALID_CONFIG_VALUE) + break; - seq_printf(s, "%d=0x%02x", dom->hdr.id, mon_info.mon_config); + seq_printf(s, "%d=0x%02x", dom->hdr.id, val); sep = true; } seq_puts(s, "\n"); @@ -1701,33 +1726,23 @@ static int mbm_local_bytes_config_show(struct kernfs_open_file *of, return 0; } -static void mon_event_config_write(void *info) -{ - struct mon_config_info *mon_info = info; - unsigned int index; - - index = mon_event_config_index_get(mon_info->evtid); - if (index == INVALID_CONFIG_INDEX) { - pr_warn_once("Invalid event id %d\n", mon_info->evtid); - return; - } - wrmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, 0); -} static void mbm_config_write_domain(struct rdt_resource *r, struct rdt_mon_domain *d, u32 evtid, u32 val) { struct mon_config_info mon_info = {0}; + u32 config_val; /* - * Read the current config value first. If both are the same then + * Check the current config value first. If both are the same then * no need to write it again. */ - mon_info.evtid = evtid; - mondata_config_read(d, &mon_info); - if (mon_info.mon_config == val) + config_val = resctrl_arch_event_config_get(d, evtid); + if (config_val == INVALID_CONFIG_VALUE || config_val == val) return; + mon_info.d = d; + mon_info.evtid = evtid; mon_info.mon_config = val; /* @@ -1736,7 +1751,8 @@ static void mbm_config_write_domain(struct rdt_resource *r, * are scoped at the domain level. Writing any of these MSRs * on one CPU is observed by all the CPUs in the domain. */ - smp_call_function_any(&d->hdr.cpu_mask, mon_event_config_write, + smp_call_function_any(&d->hdr.cpu_mask, + resctrl_arch_event_config_set, &mon_info, 1); /* diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 72c498deeb5e..ef08f75191f2 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -350,6 +350,10 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain *d, */ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *d); +void resctrl_arch_event_config_set(void *info); +u32 resctrl_arch_event_config_get(struct rdt_mon_domain *d, + enum resctrl_event_id eventid); + extern unsigned int resctrl_rmid_realloc_threshold; extern unsigned int resctrl_rmid_realloc_limit; -- 2.34.1