Re: [PATCH v2 0/6] timekeeping: Reduce magnitude of ntp_error

["Wang, Yuan1" <yuan1.wang@intel.com>]

On 11/6/2026 11:08 AM, David Woodhouse wrote:

> From: David Woodhouse <dwmw@amazon.co.uk>
>
>
> This turns out not to be theoretical: Jie Wang reports¹ that since the
> v7.3 accounting fixes, phc2sys takes minutes instead of seconds to
> settle CLOCK_REALTIME after a step of the PHC it follows, because its
> large frequency corrections are charged to ntp_error and repaid only
> through the dithering. Patch 1 of this series is the fix for that:
> Yuan Wang has measured it restoring their gPTP settling times (back to
> 32s from 200-400s or more) and withdrawn the RFC posted in that thread
> in its favour.

I tested v2 on top of v7.3 (Intel mainline-tracking v7.3; kernel/time
is identical to upstream v7.3), both the whole series and patch 1 on
its own.

Setup: two Intel i226 NICs back to back with gPTP (ptp4l + phc2sys on
each end), PREEMPT_RT, NO_HZ_FULL, HZ=1000, TSC. phc2sys reads the PHC
with PTP_SYS_OFFSET_PRECISE, so patch 6 is in the path. The
grandmaster's PHC is stepped by +1s three times, 400s apart. The
numbers are the time until the offset stays below 100ns:

                                  GM phc2sys               slave phc2sys    slave ptp4l
  v7.3                        207/>361/>413s       114/79/293s     34-35s
  v7.3 + v2 1/6         32/32/32s                  40/41/41s         34-35s
  v7.3 + v2 1-6/6     32/32/32s                  41/41/40s          34-35s

">" means it had not settled before the next step.

With either kernel, the steady-state phc2sys lock is unchanged:
7-9ns rms and below 35ns peak on both ends, before the steps and in
the second half of each 400s window. There were no warnings in dmesg
and no ioctl errors from phc2sys.

I also ran adjtime(+5ms) with nothing else adjusting the clock and
measured the phase error left once the slew has finished. With patch
1 alone it was +1.5 to +8.4us over four runs. With the whole series it
was +0.47 and +0.61us over two runs, so patches 2-3 visibly help there
too.

For the whole series:

Tested-by: Yuan Wang <yuan1.wang@intel.com>

Thanks,
Yuan