Re: [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level

[Matthias Schiffer <matthias.schiffer@ew.tq-group.com>]

On Fri, 2024-08-09 at 08:57 -0500, Logan Bristol wrote:
> 
> External interfaces should be disabled at the SoC DTSI level, since
> the node is incomplete. Disable Ethernet switch and ports in SoC DTSI 
> and enable them in the board DTS. If the board DTS includes a SoM DTSI 
> that completes the node description, enable the Ethernet switch and ports 
> in SoM DTSI.
> 
> Reflect this change in SoM DTSIs by removing ethernet port disable.
> 
> Signed-off-by: Logan Bristol <logan.bristol@utexas.edu>

For the TQMa64xxL:

Acked-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>


> ---
> Changes since v1:
> - Enabled cpsw3g and cpsw_port1 in SoM DTSI instead of board DTS
> if board DTS included SoM DTSI
> ---
>  arch/arm64/boot/dts/ti/k3-am64-main.dtsi               | 3 +++
>  arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi        | 6 ++----
>  arch/arm64/boot/dts/ti/k3-am642-evm.dts                | 3 +++
>  arch/arm64/boot/dts/ti/k3-am642-sk.dts                 | 3 +++
>  arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi            | 6 ++----
>  arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 6 ++----
>  6 files changed, 15 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> index f8370dd03350..69c5af58b727 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> @@ -677,6 +677,7 @@ cpsw3g: ethernet@8000000 {
>  		assigned-clock-parents = <&k3_clks 13 9>;
>  		clock-names = "fck";
>  		power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
> +		status = "disabled";
>  
>  		dmas = <&main_pktdma 0xC500 15>,
>  		       <&main_pktdma 0xC501 15>,
> @@ -701,6 +702,7 @@ cpsw_port1: port@1 {
>  				phys = <&phy_gmii_sel 1>;
>  				mac-address = [00 00 00 00 00 00];
>  				ti,syscon-efuse = <&main_conf 0x200>;
> +				status = "disabled";
>  			};
>  
>  			cpsw_port2: port@2 {
> @@ -709,6 +711,7 @@ cpsw_port2: port@2 {
>  				label = "port2";
>  				phys = <&phy_gmii_sel 2>;
>  				mac-address = [00 00 00 00 00 00];
> +				status = "disabled";
>  			};
>  		};
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> index ea7c58fb67e2..6bece2fb4e95 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> @@ -185,6 +185,7 @@ AM64X_IOPAD(0x0278, PIN_INPUT, 7)	/* (C19) EXTINTn.GPIO1_70 */
>  &cpsw3g {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&cpsw_rgmii1_pins_default>;
> +	status = "okay";
>  };
>  
>  &cpsw3g_mdio {
> @@ -208,10 +209,7 @@ cpsw3g_phy1: ethernet-phy@1 {
>  &cpsw_port1 {
>  	phy-mode = "rgmii-rxid";
>  	phy-handle = <&cpsw3g_phy1>;
> -};
> -
> -&cpsw_port2 {
> -	status = "disabled";
> +	status = "okay";
>  };
>  
>  &mailbox0_cluster2 {
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index 6bb1ad2e56ec..82da21bd9aea 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -616,17 +616,20 @@ &cpsw3g {
>  	bootph-all;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
> +	status = "okay";
>  };
>  
>  &cpsw_port1 {
>  	bootph-all;
>  	phy-mode = "rgmii-rxid";
>  	phy-handle = <&cpsw3g_phy0>;
> +	status = "okay";
>  };
>  
>  &cpsw_port2 {
>  	phy-mode = "rgmii-rxid";
>  	phy-handle = <&cpsw3g_phy3>;
> +	status = "okay";
>  };
>  
>  &cpsw3g_mdio {
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> index 44ecbcf1c844..86369525259c 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> @@ -527,16 +527,19 @@ &usb0 {
>  &cpsw3g {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
> +	status = "okay";
>  };
>  
>  &cpsw_port1 {
>  	phy-mode = "rgmii-rxid";
>  	phy-handle = <&cpsw3g_phy0>;
> +	status = "okay";
>  };
>  
>  &cpsw_port2 {
>  	phy-mode = "rgmii-rxid";
>  	phy-handle = <&cpsw3g_phy1>;
> +	status = "okay";
>  };
>  
>  &cpsw3g_mdio {
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> index c19d0b8bbf0f..a5cec9a07510 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> @@ -177,6 +177,7 @@ vdd_mmc0: regulator-vdd-mmc0 {
>  &cpsw3g {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&rgmii1_default_pins>;
> +	status = "okay";
>  };
>  
>  &cpsw3g_mdio {
> @@ -210,10 +211,7 @@ ethernet_phy0: ethernet-phy@0 {
>  &cpsw_port1 {
>  	phy-mode = "rgmii-id";
>  	phy-handle = <&ethernet_phy0>;
> -};
> -
> -&cpsw_port2 {
> -	status = "disabled";
> +	status = "okay";
>  };
>  
>  &icssg1_mdio {
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> index c40ad67cee01..8d7a0283c391 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> @@ -119,15 +119,13 @@ reg_sd: regulator-sd {
>  &cpsw3g {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&cpsw_pins>;
> +	status = "okay";
>  };
>  
>  &cpsw_port1 {
>  	phy-mode = "rgmii-rxid";
>  	phy-handle = <&cpsw3g_phy0>;
> -};
> -
> -&cpsw_port2 {
> -	status = "disabled";
> +	status = "okay";
>  };
>  
>  &cpsw3g_mdio {

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