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From: Abhinav Kumar <quic_abhinavk@quicinc.com>
To: Marijn Suijten <marijn.suijten@somainline.org>,
	<phone-devel@vger.kernel.org>, Rob Clark <robdclark@gmail.com>,
	"Dmitry Baryshkov" <dmitry.baryshkov@linaro.org>,
	Vinod Koul <vkoul@kernel.org>
Cc: ~postmarketos/upstreaming@lists.sr.ht,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@somainline.org>,
	"Konrad Dybcio" <konrad.dybcio@somainline.org>,
	"Martin Botka" <martin.botka@somainline.org>,
	"Jami Kettunen" <jami.kettunen@somainline.org>,
	"Sean Paul" <sean@poorly.run>, "David Airlie" <airlied@gmail.com>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"Stephen Boyd" <swboyd@chromium.org>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Jessica Zhang" <quic_jesszhan@quicinc.com>,
	"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	"Kuogee Hsieh" <quic_khsieh@quicinc.com>,
	"Jani Nikula" <jani.nikula@intel.com>,
	sunliming <sunliming@kylinos.cn>,
	"Sam Ravnborg" <sam@ravnborg.org>,
	"Haowen Bai" <baihaowen@meizu.com>,
	"Konrad Dybcio" <konrad.dybcio@linaro.org>,
	"Loic Poulain" <loic.poulain@linaro.org>,
	"Vinod Polimera" <quic_vpolimer@quicinc.com>,
	"Douglas Anderson" <dianders@chromium.org>,
	"Vladimir Lypak" <vladimir.lypak@gmail.com>,
	linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 2/6] drm/msm/dpu1: Add DSC config for sm8150 and sm8250
Date: Fri, 16 Dec 2022 12:53:08 -0800	[thread overview]
Message-ID: <cee94281-07a5-42b7-3d60-6ef6367ff915@quicinc.com> (raw)
In-Reply-To: <20221213232207.113607-3-marijn.suijten@somainline.org>



On 12/13/2022 3:22 PM, Marijn Suijten wrote:
> These blocks on CTL V1 support setting a PINGPONG idx to send pixel
> output to.
> 
> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
>   .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 23 ++++++++++++++-----
>   1 file changed, 17 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 318f0b4dbf6e..114ad8ca4554 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -1566,18 +1566,25 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
>   /*************************************************************
>    * DSC sub blocks config
>    *************************************************************/
> -#define DSC_BLK(_name, _id, _base) \
> +#define DSC_BLK(_name, _id, _base, _features) \
>   	{\
>   	.name = _name, .id = _id, \
>   	.base = _base, .len = 0x140, \
> -	.features = 0, \
> +	.features = _features, \
>   	}
>   
>   static struct dpu_dsc_cfg sdm845_dsc[] = {
> -	DSC_BLK("dsc_0", DSC_0, 0x80000),
> -	DSC_BLK("dsc_1", DSC_1, 0x80400),
> -	DSC_BLK("dsc_2", DSC_2, 0x80800),
> -	DSC_BLK("dsc_3", DSC_3, 0x80c00),
> +	DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
> +	DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
> +	DSC_BLK("dsc_2", DSC_2, 0x80800, 0),
> +	DSC_BLK("dsc_3", DSC_3, 0x80c00, 0),
> +};
> +
> +static struct dpu_dsc_cfg sm8150_dsc[] = {
> +	DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
> +	DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
> +	DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
> +	DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
>   };
>   
>   /*************************************************************
> @@ -2474,6 +2481,8 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
>   	.mixer = sm8150_lm,
>   	.dspp_count = ARRAY_SIZE(sm8150_dspp),
>   	.dspp = sm8150_dspp,
> +	.dsc_count = ARRAY_SIZE(sm8150_dsc),
> +	.dsc = sm8150_dsc,
>   	.pingpong_count = ARRAY_SIZE(sm8150_pp),
>   	.pingpong = sm8150_pp,
>   	.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
> @@ -2524,6 +2533,8 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
>   	.mixer = sm8150_lm,
>   	.dspp_count = ARRAY_SIZE(sm8150_dspp),
>   	.dspp = sm8150_dspp,
> +	.dsc_count = ARRAY_SIZE(sm8150_dsc),
> +	.dsc = sm8150_dsc,
>   	.pingpong_count = ARRAY_SIZE(sm8150_pp),
>   	.pingpong = sm8150_pp,
>   	.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),

  parent reply	other threads:[~2022-12-16 20:53 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-13 23:22 [RFC PATCH 0/6] drm/msm: DSC Electric Boogaloo for sm8[12]50 Marijn Suijten
2022-12-13 23:22 ` [RFC PATCH 1/6] drm/msm/dpu1: Implement DSC binding to PP block for CTL V1 Marijn Suijten
2022-12-14 18:40   ` Dmitry Baryshkov
2022-12-16 20:51   ` Abhinav Kumar
2022-12-13 23:22 ` [RFC PATCH 2/6] drm/msm/dpu1: Add DSC config for sm8150 and sm8250 Marijn Suijten
2022-12-14 18:42   ` Dmitry Baryshkov
2022-12-16 20:53   ` Abhinav Kumar [this message]
2022-12-13 23:22 ` [RFC PATCH 3/6] drm/msm/dpu1: Wire up DSC mask for active CTL configuration Marijn Suijten
2022-12-14 18:43   ` Dmitry Baryshkov
2022-12-14 19:30     ` Marijn Suijten
2022-12-15  1:08       ` Dmitry Baryshkov
2022-12-16 22:20         ` Abhinav Kumar
2022-12-20 22:32           ` Marijn Suijten
2022-12-13 23:22 ` [RFC PATCH 4/6] drm/msm/dsi: Use DSC slice(s) packet size to compute word count Marijn Suijten
2022-12-14 18:52   ` Dmitry Baryshkov
2022-12-16 23:01   ` Abhinav Kumar
2022-12-13 23:22 ` [RFC PATCH 5/6] drm/msm/dsi: Flip greater-than check for slice_count and slice_per_intf Marijn Suijten
2022-12-14  0:02   ` Konrad Dybcio
2022-12-14  8:38     ` Marijn Suijten
2022-12-14 18:53   ` Dmitry Baryshkov
2022-12-17  0:31   ` Abhinav Kumar
2022-12-13 23:22 ` [RFC PATCH 6/6] drm/msm/dpu: Disallow unallocated (DSC) resources to be returned Marijn Suijten
2022-12-14 18:56   ` Dmitry Baryshkov
2022-12-14 19:31     ` Marijn Suijten
2022-12-14 18:40 ` [RFC PATCH 0/6] drm/msm: DSC Electric Boogaloo for sm8[12]50 Dmitry Baryshkov
2022-12-14 19:23   ` Marijn Suijten
2022-12-15  0:52     ` Dmitry Baryshkov
2022-12-20 22:35       ` Marijn Suijten

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