From: Len Brown <lenb@kernel.org>
To: x86@kernel.org
Cc: linux-kernel@vger.kernel.org, Len Brown <len.brown@intel.com>
Subject: [PATCH 03/10] x86 tsc_msr: Remove debugging messages
Date: Fri, 17 Jun 2016 01:22:45 -0400 [thread overview]
Message-ID: <cf03279a125b95dfa9b8d3d5b4a66de09cd04050.1466138954.git.len.brown@intel.com> (raw)
In-Reply-To: <20160617052252.25991-1-lenb@kernel.org>
In-Reply-To: <2199d0e959f7f71a18827268b5d060f8d3831639.1466138954.git.len.brown@intel.com>
From: Len Brown <len.brown@intel.com>
Debugging messages are not necessary after all of the
possible hardware failures that never occur.
Instead, this code can simply return 0.
This code also doesn't need to print in the success case.
tsc_init() already prints the TSC frequency,
and apic=debug is available if anybody really is
interested in printing the LAPIC frequency.
Signed-off-by: Len Brown <len.brown@intel.com>
---
arch/x86/kernel/tsc_msr.c | 19 +++----------------
1 file changed, 3 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 4ec5e56..f7ba44b 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -76,9 +76,10 @@ static int match_cpu(u8 family, u8 model)
(freq_desc_tables[cpu_index].freqs[freq_id])
/*
- * Do MSR calibration only for known/supported CPUs.
+ * MSR-based CPU/TSC frequency discovery for certain CPUs.
*
- * Returns the calibration value or 0 if MSR calibration failed.
+ * Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy
+ * Return processor base frequency in KHz, or 0 on failure.
*/
unsigned long try_msr_calibrate_tsc(void)
{
@@ -100,31 +101,17 @@ unsigned long try_msr_calibrate_tsc(void)
rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
ratio = (hi >> 8) & 0x1f;
}
- pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
-
- if (!ratio)
- goto fail;
/* Get FSB FREQ ID */
rdmsr(MSR_FSB_FREQ, lo, hi);
freq_id = lo & 0x7;
freq = id_to_freq(cpu_index, freq_id);
- pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
- freq_id, freq);
- if (!freq)
- goto fail;
/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
res = freq * ratio;
- pr_info("TSC runs at %lu KHz\n", res);
#ifdef CONFIG_X86_LOCAL_APIC
lapic_timer_frequency = (freq * 1000) / HZ;
- pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
#endif
return res;
-
-fail:
- pr_warn("Fast TSC calibration using MSR failed\n");
- return 0;
}
--
2.9.0
next prev parent reply other threads:[~2016-06-17 5:23 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-17 5:22 [PATCH 0/10] x86/tsc: fast calibration updates Len Brown
2016-06-17 5:22 ` [PATCH 01/10] Revert "x86/tsc: Add missing Cherrytrail frequency to the table" Len Brown
2016-06-17 5:22 ` [PATCH 02/10] x86 tsc_msr: Identify Intel-specific code Len Brown
2016-07-10 18:10 ` [tip:x86/timers] x86/tsc_msr: " tip-bot for Len Brown
2016-06-17 5:22 ` Len Brown [this message]
2016-07-10 18:10 ` [tip:x86/timers] x86/tsc_msr: Remove debugging messages tip-bot for Len Brown
2016-06-17 5:22 ` [PATCH 04/10] x86 tsc_msr: Update comments, expand definitions Len Brown
2016-07-10 18:11 ` [tip:x86/timers] x86/tsc_msr: " tip-bot for Len Brown
2016-06-17 5:22 ` [PATCH 05/10] x86 tsc_msr: Correct Silvermont reference clock values Len Brown
2016-07-10 18:11 ` [tip:x86/timers] x86/tsc_msr: " tip-bot for Len Brown
2016-06-17 5:22 ` [PATCH 06/10] x86 tsc_msr: Add Airmont " Len Brown
2016-07-10 18:12 ` [tip:x86/timers] x86/tsc_msr: " tip-bot for Len Brown
2016-06-17 5:22 ` [PATCH 07/10] x86 tsc_msr: Extend to include Intel Core Architecture Len Brown
2016-07-10 18:12 ` [tip:x86/timers] x86/tsc_msr: " tip-bot for Len Brown
2016-06-17 5:22 ` [PATCH 08/10] x86 tsc_msr: Remove irqoff around MSR-based TSC enumeration Len Brown
2016-07-10 18:12 ` [tip:x86/timers] x86/tsc_msr: " tip-bot for Len Brown
2016-07-11 19:33 ` tip-bot for Len Brown
2016-06-17 5:22 ` [PATCH 09/10] x86 tsc: enumerate SKL cpu_khz and tsc_khz via CPUID Len Brown
2016-07-10 18:13 ` [tip:x86/timers] x86/tsc: Enumerate " tip-bot for Len Brown
2016-07-11 19:34 ` tip-bot for Len Brown
2016-06-17 5:22 ` [PATCH 10/10] x86 tsc: enumerate BXT " Len Brown
2016-07-10 18:13 ` [tip:x86/timers] x86/tsc: Enumerate " tip-bot for Len Brown
2016-07-11 19:34 ` tip-bot for Len Brown
2016-07-10 18:09 ` [tip:x86/timers] Revert "x86/tsc: Add missing Cherrytrail frequency to the table" tip-bot for Len Brown
2016-06-17 7:36 ` [PATCH 0/10] x86/tsc: fast calibration updates Thomas Gleixner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cf03279a125b95dfa9b8d3d5b4a66de09cd04050.1466138954.git.len.brown@intel.com \
--to=lenb@kernel.org \
--cc=len.brown@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®