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Tue, 27 Oct 2026 21:54:58 -0700 (PDT) Received: from [10.217.216.70] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a2396276asm2031284eec.22.2026.10.27.21.54.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Oct 2026 21:54:57 -0700 (PDT) Message-ID: Date: Wed, 28 Oct 2026 10:24:38 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Imran Shaik Subject: Re: [PATCH 1/6] dt-bindings: ptp: Document the TSCSS on Qualcomm Lemans and Monaco SoCs To: Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bjorn Andersson , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org References: <20260727-tscss-v1-0-beed14e72510@oss.qualcomm.com> <20260727-tscss-v1-1-beed14e72510@oss.qualcomm.com> <02792987-7ad8-4a6b-81ad-559c63174bb0@kernel.org> <640acacb-1704-4ee6-aa34-d6be3b30b44b@oss.qualcomm.com> <7f6839fb-59b0-4f6d-a3f8-7579f6d40857@oss.qualcomm.com> <237b2f74-4a9b-4df2-a0fe-a7b783ed5267@oss.qualcomm.com> <8fdc66b2-6047-4f3d-932f-1e6883e370bc@kernel.org> Content-Language: en-US In-Reply-To: <8fdc66b2-6047-4f3d-932f-1e6883e370bc@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: cNqC16eluSOmR9XdB-kF9-SPxp4VBwLV X-Authority-Analysis: v=2.4 cv=HeuB3SE8 c=1 sm=1 tr=0 ts=6ae18023 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=bmQgafSgubap5fUq5zoA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI4MDAxOSBTYWx0ZWRfX4BjDaGbBFoVe hfbyQDg7d2twtNhA7rB3N2eoVFNWgXR0H8XELIhzxQc+VVT/RYc9bxae/H77cuJLO3f7TAii6mc RWsTSBDs/sWFnSWEvnlO4aCPXzdqogU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI4MDAxOSBTYWx0ZWRfX7OgOb32gARSz 70vwPkL/0OPNxGqyXf9awQmmTMZdVMzrFEYGR5radYQFO5yaWEvw48ptoQdctyJE3EeyY+Ho/p/ poc+VS0asP+eJjHYhMA/AkGVbts0LRXjTgEurKyq1PpKyhX/1H4n26HiDvnm3KoEue5y7YKqMqr mSNNcVHodmIYxhY3DhD3AXQwADIhW3wDm0RqkHbwJVVbCFbD3ZKh1TMuDJ0fYYzjiH87KWb02fp RV9byYIM16rTBDc0XrEW5h4XvUCz8ajoJIuXK/4jBd5rDD3oGNX3Gp5Vu4vHTDRD3alrnMqJC5n 5U6pvW71diW1KUC7CwLkjIw6j46EeNOZKTy5SVCHhCT/AVPym/0H1ySk0jinjctMwCG6RlSfkK+ zNd3T5250JS4uwh2ZFcWIaWknrlbInPGekeIoomcvEGQkvp9SaFF5BUhGFJs9eVttTMm2NleQyu dYsxpWmbzn8SPHtiZRQ== X-Proofpoint-GUID: cNqC16eluSOmR9XdB-kF9-SPxp4VBwLV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-28_02,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 phishscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610280019 On 27-10-2026 08:49 pm, Krzysztof Kozlowski wrote: > On 26/10/2026 13:55, Imran Shaik wrote: >>> >>>> >>>> On checking further, I found that our etu-slice sub node deviates from >>>> that example, since we don't have a compatible string for the sub node. >>>> >>>> Please let me know if we should move the pinctrl properties under the >>>> tscss node with per-slice names, or instead keep them under the >>>> etu-slice sub node and add a compatible there. >>> >>> etu-slice does not feel like device at all unfortunately. I see only >>> address space, so one resource, which might be enough but lack of >>> description for the subnode is not helping. I have doubts that separate >>> subnodes should be there in the first place, but if they stay, describe >>> the child node fully - what sort of device it is. Just because there is >>> independent timestamping counter does not make it separate device, just >>> like independent interrupt in GIC is not itself an independent device. >>> >> >> The ETU is an independent hardware block within TSCSS that captures/ > > How is it independent? I see no resources, except address space. A > channel of some device does not mean it is a separate device. > Sure, got it. > >> snapshots the TSC timestamp in response to an external hardware >> event trigger, for each slice individually. Hence the subnodes approach >> was followed and will capture these details in the description as well. >> >> If we drop the subnodes and add everything into the parent TSCSS node >> instead, then all the arrays here must stay index aligned as per slice >> mapping. Example DTS node looks like this (QDU1000, 3 slices): >> >> ptp@1da0000 { >> compatible = "qcom,qdu1000-tscss"; >> reg = <0x0 0x01da0000 0x0 0x2000>, >> <0x0 0x01db0000 0x0 0x10000>; >> reg-names = "tsc", "etu"; >> >> ... >> >> interrupts = , >> , >> ; >> interrupt-names = "slice1", "slice5", "slice6"; >> >> pinctrl-0 = <&tod_pps>; >> pinctrl-1 = <&gps_pps>; >> pinctrl-2 = <&hardsync_pps>; >> pinctrl-names = "slice1", "slice5", "slice6"; >> >> qcom,etu-slice = <1 5 6>; >> qcom,etu-event-sel = <1 3 2>; > > Why this is not continuous? The slices are all fixed in the hardware. I > don't get why do you list some of them. > The slices are fixed and contiguous in hardware (e.g. QDU1000 has 16 ETU slices, 0-15), and accordingly will describe the bindings. But based on vendor/target board requirements, the slice configuration can use all 16 or only a few, and might not be continuous. If the board requirement is to get the external hardware event sourced via certain GPIOs based on the availability, then accordingly, the ETU slice and respective event sel needs to be configured. In the example, slice 1, 5 and 6 are used to route TOD PPS, GPS PPS and hardsync PPS pins respectively on QDU1000 SoC, and the remaining slices are not used. Thanks, Imran