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Wed, 30 Apr 2025 20:40:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHW6a/uU1DCKjMX5JLHAC9khf/wySTJvMqlUsZIdvGKjmMukBMZ9FoZF/x8NrqKxPW33mJK9A== X-Received: by 2002:a17:903:18e:b0:224:10a2:cad5 with SMTP id d9443c01a7336-22e040a2e4fmr26932325ad.10.1746070811228; Wed, 30 Apr 2025 20:40:11 -0700 (PDT) Received: from [192.168.68.51] ([180.233.125.65]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db51051c6sm130511945ad.206.2025.04.30.20.40.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Apr 2025 20:40:10 -0700 (PDT) Message-ID: Date: Thu, 1 May 2025 13:40:01 +1000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 34/43] arm64: RME: Propagate number of breakpoints and watchpoints to userspace From: Gavin Shan To: Steven Price , kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Jean-Philippe Brucker , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" References: <20250416134208.383984-1-steven.price@arm.com> <20250416134208.383984-35-steven.price@arm.com> <19ec5533-ee10-4670-a9fd-da1345a6946a@redhat.com> Content-Language: en-US In-Reply-To: <19ec5533-ee10-4670-a9fd-da1345a6946a@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 5/1/25 1:36 PM, Gavin Shan wrote: > On 4/16/25 11:41 PM, Steven Price wrote: >> From: Jean-Philippe Brucker >> >> The RMM describes the maximum number of BPs/WPs available to the guest >> in the Feature Register 0. Propagate those numbers into ID_AA64DFR0_EL1, >> which is visible to userspace. A VMM needs this information in order to >> set up realm parameters. >> >> Signed-off-by: Jean-Philippe Brucker >> Signed-off-by: Steven Price >> --- >>   arch/arm64/include/asm/kvm_rme.h |  2 ++ >>   arch/arm64/kvm/rme.c             | 22 ++++++++++++++++++++++ >>   arch/arm64/kvm/sys_regs.c        |  2 +- >>   3 files changed, 25 insertions(+), 1 deletion(-) >> > > If I don't miss anything, it's not enough to apply the filter on reading and > resetting path where sanitise_id_aa64dfr0_el1() is called. id_aa64dfr0_el1 > is writable and it's possible that QEMU modifies its value. Afterwards, the > register is read from guest kernel, which will be trapped to host and the > modified value is returned, without this filter applied. So I think the same > filter need to be applied to the write path originated from QEMU. > Please ignore this and it has been done in next patch :) Thanks, Gavin >> diff --git a/arch/arm64/include/asm/kvm_rme.h b/arch/arm64/include/asm/kvm_rme.h >> index f786fd978cf6..09cbb61816f3 100644 >> --- a/arch/arm64/include/asm/kvm_rme.h >> +++ b/arch/arm64/include/asm/kvm_rme.h >> @@ -94,6 +94,8 @@ void kvm_init_rme(void); >>   u32 kvm_realm_ipa_limit(void); >>   u32 kvm_realm_vgic_nr_lr(void); >> +u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); >> + >>   bool kvm_rme_supports_sve(void); >>   int kvm_realm_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap); >> diff --git a/arch/arm64/kvm/rme.c b/arch/arm64/kvm/rme.c >> index 297b13ef1729..0c358ce0a7a1 100644 >> --- a/arch/arm64/kvm/rme.c >> +++ b/arch/arm64/kvm/rme.c >> @@ -87,6 +87,28 @@ u32 kvm_realm_vgic_nr_lr(void) >>       return u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_GICV3_NUM_LRS); >>   } >> +u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) >> +{ >> +    u32 bps = u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_NUM_BPS); >> +    u32 wps = u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_NUM_WPS); >> +    u32 ctx_cmps; >> + >> +    if (!kvm_is_realm(vcpu->kvm)) >> +        return val; >> + >> +    /* Ensure CTX_CMPs is still valid */ >> +    ctx_cmps = FIELD_GET(ID_AA64DFR0_EL1_CTX_CMPs, val); >> +    ctx_cmps = min(bps, ctx_cmps); >> + >> +    val &= ~(ID_AA64DFR0_EL1_BRPs_MASK | ID_AA64DFR0_EL1_WRPs_MASK | >> +         ID_AA64DFR0_EL1_CTX_CMPs); >> +    val |= FIELD_PREP(ID_AA64DFR0_EL1_BRPs_MASK, bps) | >> +           FIELD_PREP(ID_AA64DFR0_EL1_WRPs_MASK, wps) | >> +           FIELD_PREP(ID_AA64DFR0_EL1_CTX_CMPs, ctx_cmps); >> + >> +    return val; >> +} >> + >>   static int get_start_level(struct realm *realm) >>   { >>       return 4 - ((realm->ia_bits - 8) / (RMM_PAGE_SHIFT - 3)); >> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >> index de7fe024dbff..36e22ed84e7e 100644 >> --- a/arch/arm64/kvm/sys_regs.c >> +++ b/arch/arm64/kvm/sys_regs.c >> @@ -1844,7 +1844,7 @@ static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) >>       /* Hide BRBE from guests */ >>       val &= ~ID_AA64DFR0_EL1_BRBE_MASK; >> -    return val; >> +    return kvm_realm_reset_id_aa64dfr0_el1(vcpu, val); >>   } >>   static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, >