From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A31E372B49 for ; Tue, 17 Feb 2026 18:51:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771354266; cv=none; b=NXeD6anXhDJqnv96atWzQkWjzV+2N1uRc0GD0FmCXFrMZxYVqdzqBqD6XqDhXLuC+sNdoveuD2YvAMAANnankhTzYvyJwIoO1P7fJ6q0GawIfd6G15iXYEPrqcW8giBwyr/YlqRseiJb633yWR2iAI8cPVgPvFFdzymkaFPciXU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771354266; c=relaxed/simple; bh=wVrNozVb4uMNWGjpXbvLfDH03NZIfrKIac17VUx3+7w=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=jhUuUbCU80lH149wv+WMyhSXYdpKXI5287MV+bbDfF+DA7I79OY+Gp3NOCd7A8MxFApGMWXEv5ulJH+cFVW/a5jKdAT/A8FXbdOwHpX4qnqRGmmlWDYl0v5bO0Q3NeWmbXS5CP7h/G3/xQvCWKL3PjPx+ZwFEzq2XbPe9YvVArw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RArWZ4A0; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RArWZ4A0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1771354265; x=1802890265; h=message-id:subject:from:to:cc:date:in-reply-to: references:content-transfer-encoding:mime-version; bh=wVrNozVb4uMNWGjpXbvLfDH03NZIfrKIac17VUx3+7w=; b=RArWZ4A0YJyrYq+bp66ph2wJ1xOeDso01qY5482vLLugk0m9zVE+Q/QX yCtD3QaVloOZZLglAQp4UzIXtpzgyjuEy1OZd2BW7GGpqW0z1l3bOsP+d bBbymIBKLaFwAdZFsgo4VH7qWIMJZ/W6PseVjr6C5pq7vdYVd6y/UuNo5 AjGCQa+wFFEE46Im6fR0wJn0uISxSawg47Ut+kz2fW8/uvZxLRCHPYvpW sxW1uzCa7vagwqR6F1fp1UIvkN2c4KuZ9hRQRrT9k7DemOMhg2KJ/vmnL qlrixQ9cC8X86oHSlTNiaG61w6qy6TAB+ruW70GvfAT31EYtpxTCHL6KF g==; X-CSE-ConnectionGUID: S8nPwWA8QCy9HFoyINUknw== X-CSE-MsgGUID: yCZTJdDwRGmR0Q7mv7wGCA== X-IronPort-AV: E=McAfee;i="6800,10657,11704"; a="95061159" X-IronPort-AV: E=Sophos;i="6.21,296,1763452800"; d="scan'208";a="95061159" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2026 10:51:04 -0800 X-CSE-ConnectionGUID: xzv5QilhTdWGq7sYaxXiTA== X-CSE-MsgGUID: dkfRth36Qo6MCOGqSMOl4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,296,1763452800"; d="scan'208";a="218107712" Received: from unknown (HELO [10.241.243.83]) ([10.241.243.83]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2026 10:51:04 -0800 Message-ID: Subject: Re: [PATCH v3 01/21] sched/cache: Introduce infrastructure for cache-aware load balancing From: Tim Chen To: "Chen, Yu C" , Madadi Vineeth Reddy Cc: Peter Zijlstra , Ingo Molnar , K Prateek Nayak , "Gautham R . Shenoy" , Vincent Guittot , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , linux-kernel@vger.kernel.org Date: Tue, 17 Feb 2026 10:51:03 -0800 In-Reply-To: References: <6ec6eee6e1c620c0cfb9f56923f8bfbb71c31a75.1770760558.git.tim.c.chen@linux.intel.com> <7c0ff4c8-5529-48de-843f-612732553aff@linux.ibm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.1 (3.58.1-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Sat, 2026-02-14 at 23:34 +0800, Chen, Yu C wrote: > Hi Vineeth, >=20 > On 2/14/2026 8:26 PM, Madadi Vineeth Reddy wrote: > > Hi Tim, > > Thanks for the patch series. > >=20 > > On 11/02/26 03:48, Tim Chen wrote: > > > From: "Peter Zijlstra (Intel)" > > >=20 > > > Adds infrastructure to enable cache-aware load balancing, > > > which improves cache locality by grouping tasks that share resources > > > within the same cache domain. This reduces cache misses and improves > > > overall data access efficiency. > >=20 > > [..snip..] > >=20 > > > +void mm_init_sched(struct mm_struct *mm, > > > + struct sched_cache_time __percpu *_pcpu_sched) > > > +{ > > > + unsigned long epoch; > > > + int i; > > > + > > > + for_each_possible_cpu(i) { > > > + struct sched_cache_time *pcpu_sched =3D per_cpu_ptr(_pcpu_sched, i= ); > > > + struct rq *rq =3D cpu_rq(i); > > > + > > > + pcpu_sched->runtime =3D 0; > > > + pcpu_sched->epoch =3D rq->cpu_epoch; > > > + epoch =3D rq->cpu_epoch; > >=20 > > Shouldn't cpu_epoch be read under cpu_epoch_lock, similar to how fracti= on_mm_sched() > > and __update_mm_sched() acquire the lock before accessing this field? >=20 > My understanding is that __update_mm_sched() updates rq->cpu_epoch in=20 > two steps: > first, it reads the current value, and then it writes the new value back= =20 > to it > (as seen in the operation rq->cpu_epoch +=3D n). For this reason, a lock= =20 > is required > to prevent race conditions during concurrent updates across multiple CPUs= . >=20 > In contrast, reading rq->cpu_epoch in mm_init_sched() is a single atomic= =20 > operation, > and it is acceptable to read a stale value in this scenario - thus, we= =20 > can safely > perform an unprotected read of this field here. >=20 There is no particular advantage to prevent cpu_epoch update during mm initialization by holding the cpu_epoch lock. The difference with using a slightly stale cpu epoch will=C2=A0be one epoch in __update_mm_sched() which will be quickly aged out in the subsequent updates.=C2=A0 However holding the lock could affect scalability and slow down workload th= at forks short lived processes frequently and hence the choice. Tim