From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=113.46.200.223 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793083551; b=UF0ubxofouZe0LUJ4Yjk5AtswyB6ItdebILbJzO3Y8D6seQ5/AcbqKE0++FIdzo9DRf5 EC1CCsjU8t0+McPXXBdOKjlywRfiSag16fiDzS9zzqK3a8Ogrd042rxOAf5Jk2obpPwio 61b68fyzMpK19HxMh2fa2ccdVUcV79zamGWlGLH5AJAC2lueEi1c/7KsgG1JYwBWU4g1J pAn8YwfnWIQGDij5LPpcx/U5u1uO30xLJY1TweAAGU7JOwD0z5+OcHpeU5FJKkIjpKy/h bHfIjtoHmbpK5PQNmGC9udW8EgP/sNzkYfDMdYoUC1mqIiI05E/tHBLyrwJKnXnL1Zw== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793083551; h=DMARC-Filter:dkim-signature:Received:Received:Received:Message-ID: Date:MIME-Version:User-Agent:Subject:To:CC:References:From: In-Reply-To:Content-Type:Content-Transfer-Encoding:X-Originating-IP: X-ClientProxiedBy; bh=45EA+yxw9ZAYEmsBHhVFqQBnIpsw1+TN7/vvynIibe4=; b=0+ZVw1EWhYv7RjiRPlAtZ12mQrYvkv/PEXPAqVvD9iJtTujDT+l7BPeQ9steB+b1EjPO 36a8o6GIuvndMxZQm/vDSn5ugAV8GuZcSCPQmqQ2a1zaSTP/MKJtPqyKeniJ6z9+ROKAl 2xxm9Xe0FLf4ocWdDMaurh9yaKwfjv2szX5cAvbjx/35IIQTlWNF0rcf2sN21B7Wu7XT8 pMTqtob/tNE3eE9WdmwkxDqLnxdPcDqE+yFbgEkS3wxZ09gr0MIznBw6Vq1vWCoGtWOBy lpCY5FHx238Rm4RISdBS3Z3hqnmGhm5lWIJcSRjp/fT59p+ALj7gh4Yg7BHCNXZRaMg== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256 header.s=dkim header.b=s13F4IuL; arc=none smtp.remote-ip=113.46.200.223 Received: from canpmsgout08.his.huawei.com (canpmsgout08.his.huawei.com [113.46.200.223]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF05D606A31A; Tue, 27 Oct 2026 06:45:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org EF05D606A31A Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key, unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256 header.s=dkim header.b=s13F4IuL dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=45EA+yxw9ZAYEmsBHhVFqQBnIpsw1+TN7/vvynIibe4=; b=s13F4IuLINF+M1GqDP99tRvU+7xUR12+blUeguu8UXYNAvB3FzQAc7s8zAtqx2/mfQU0o6Sw/ 4NmraHb1g4xjRi381EH47uRoreLcgqUmE3pTg6e8OQyB+fySmqMIx37NUUr5+eZhJUhYFWi+RD6 zqNWHJVNSlBLYC4MdLseAbs= Received: from mail.maildlp.com (unknown [172.19.163.15]) by canpmsgout08.his.huawei.com (SkyGuard) with ESMTPS id 4jDLbk3czJzmVXl; Tue, 27 Oct 2026 14:45:38 +0800 (CST) Received: from kwepemo100017.china.huawei.com (unknown [7.202.195.215]) by mail.maildlp.com (Postfix) with ESMTPS id 29E6040578; Tue, 27 Oct 2026 14:45:44 +0800 (CST) Received: from [10.67.120.228] (10.67.120.228) by kwepemo100017.china.huawei.com (7.202.195.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Tue, 27 Oct 2026 14:45:43 +0800 Message-ID: Date: Tue, 27 Oct 2026 14:45:42 +0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4] i2c: hisi: Add I2C bus recovery support To: , , , , CC: , , , , References: <20260917024018.3052954-1-yubowen8@huawei.com> From: "yubowen (H)" In-Reply-To: <20260917024018.3052954-1-yubowen8@huawei.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemo100017.china.huawei.com (7.202.195.215) Quick ping on this. Any throughts or suggestions, or anything else you'd like me to dig into? Regards Bowen Yu 在 2026/9/17 10:40, Bowen Yu 写道: > When the I2C bus is stuck due to a slave device holding SDA low > (e.g. during an incomplete transfer), the master has no way to recover > the bus through normal operation. Add bus recovery support using the > subctrl register to manually toggle SCL and generate clock pulses to > release the bus. > > The recovery is performed via a second register resource (sctrl_base) > that provides direct control over SCL/SDA lines through mux and > output-enable bits. After recovery, the I2C controller is reset through > the ACPI _RST method and reconfigured. > > Recovery is only registered when the subctrl resource is provided in > the firmware description, keeping backward compatibility with existing > platforms. > > Signed-off-by: Bowen Yu > --- > v3 -> v4: > -Some clean code fixes. > --- > drivers/i2c/busses/i2c-hisi.c | 146 ++++++++++++++++++++++++++++++++++ > 1 file changed, 146 insertions(+) > > diff --git a/drivers/i2c/busses/i2c-hisi.c b/drivers/i2c/busses/i2c-hisi.c > index ba5c9579ae19..051a7759bb14 100644 > --- a/drivers/i2c/busses/i2c-hisi.c > +++ b/drivers/i2c/busses/i2c-hisi.c > @@ -5,6 +5,7 @@ > * Copyright (c) 2021 HiSilicon Technologies Co., Ltd. > */ > > +#include > #include > #include > #include > @@ -62,6 +63,8 @@ > #define HISI_I2C_INT_CLR 0x0048 > #define HISI_I2C_INT_MASK 0x004C > #define HISI_I2C_TRANS_STATE 0x0050 > +#define HISI_I2C_TRANS_STATE_SDA_LEVEL BIT(5) > +#define HISI_I2C_TRANS_STATE_SCL_LEVEL BIT(6) > #define HISI_I2C_TRANS_ERR 0x0054 > #define HISI_I2C_VERSION 0x0058 > > @@ -86,9 +89,26 @@ > #define NSEC_TO_CYCLES(ns, clk_rate_khz) \ > DIV_ROUND_UP_ULL((clk_rate_khz) * (ns), NSEC_PER_MSEC) > > +/* > + * SUBCTRL SC_I2C_CTRL register > + * Set HISI_I2C_CTRL_DAT_CFG_EN and HISI_I2C_CTRL_SCL_CFG_EN to control > + * I2C pin behavior by subctrl controller; use HISI_I2C_CTRL_DAT_OE and > + * HISI_I2C_CTRL_CLK_OE to control input or output; use HISI_I2C_CTRL_SDA_OUT > + * and HISI_I2C_CTRL_SCL_OUT to control output value. > + */ > +#define HISI_I2C_CTRL_DAT_CFG_EN BIT(5) > +#define HISI_I2C_CTRL_SCL_CFG_EN BIT(4) > +#define HISI_I2C_CTRL_DAT_OE BIT(3) > +#define HISI_I2C_CTRL_CLK_OE BIT(2) > +#define HISI_I2C_CTRL_SDA_OUT BIT(1) > +#define HISI_I2C_CTRL_SCL_OUT BIT(0) > + > +#define HISI_I2C_RECOVERY_REG_SIZE 4 > + > struct hisi_i2c_controller { > struct i2c_adapter adapter; > void __iomem *iobase; > + void __iomem *sctrl_addr; > struct device *dev; > struct clk *clk; > int irq; > @@ -108,8 +128,14 @@ struct hisi_i2c_controller { > struct i2c_timings t; > u32 clk_rate_khz; > u32 spk_len; > + > + /* Bus recovery */ > + struct i2c_bus_recovery_info rinfo; > + acpi_handle acpi_handle; > }; > > +static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr); > + > static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask) > { > writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); > @@ -151,6 +177,122 @@ static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr) > } > } > > +#ifdef CONFIG_ACPI > +static int hisi_i2c_recovery_get_scl(struct i2c_adapter *adap) > +{ > + struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); > + u32 reg = readl(ctlr->iobase + HISI_I2C_TRANS_STATE); > + > + return !!(reg & HISI_I2C_TRANS_STATE_SCL_LEVEL); > +} > + > +static int hisi_i2c_recovery_get_sda(struct i2c_adapter *adap) > +{ > + struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); > + u32 reg = readl(ctlr->iobase + HISI_I2C_TRANS_STATE); > + > + return !!(reg & HISI_I2C_TRANS_STATE_SDA_LEVEL); > +} > + > +static void hisi_i2c_recovery_set_scl(struct i2c_adapter *adap, int val) > +{ > + struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); > + u32 reg; > + > + reg = readl(ctlr->sctrl_addr); > + if (val) > + reg |= HISI_I2C_CTRL_SCL_OUT; > + else > + reg &= ~HISI_I2C_CTRL_SCL_OUT; > + writel(reg, ctlr->sctrl_addr); > +} > + > +static void hisi_i2c_prepare_recovery(struct i2c_adapter *adap) > +{ > + struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); > + u32 reg; > + > + reg = readl(ctlr->sctrl_addr); > + reg |= HISI_I2C_CTRL_SCL_CFG_EN | HISI_I2C_CTRL_DAT_CFG_EN | > + HISI_I2C_CTRL_CLK_OE | HISI_I2C_CTRL_SCL_OUT; > + reg &= ~HISI_I2C_CTRL_DAT_OE; > + writel(reg, ctlr->sctrl_addr); > +} > + > +static void hisi_i2c_unprepare_recovery(struct i2c_adapter *adap) > +{ > + struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); > + u32 reg; > + > + reg = readl(ctlr->sctrl_addr); > + reg &= ~(HISI_I2C_CTRL_SCL_CFG_EN | HISI_I2C_CTRL_DAT_CFG_EN); > + writel(reg, ctlr->sctrl_addr); > + > + /* > + * Invokes the specific ACPI method "_RST" to trigger a soft reset > + * of the I2C controller to help the I2C controller recover from > + * the abnormal state after the bus recovery process. > + */ > + if (ctlr->acpi_handle && acpi_has_method(ctlr->acpi_handle, "_RST")) { > + acpi_status status; > + > + status = acpi_evaluate_object(ctlr->acpi_handle, "_RST", NULL, NULL); > + if (ACPI_FAILURE(status)) > + dev_err(ctlr->dev, "_RST method failed: %s\n", > + acpi_format_exception(status)); > + } > + hisi_i2c_configure_bus(ctlr); > +} > + > +static int hisi_i2c_get_bus_recovery_res(struct hisi_i2c_controller *ctlr, > + struct platform_device *pdev) > +{ > + struct resource *res0; > + > + res0 = platform_get_resource(pdev, IORESOURCE_MEM, 1); > + > + if (!res0 || resource_size(res0) != HISI_I2C_RECOVERY_REG_SIZE) > + return -ENODEV; > + > + ctlr->sctrl_addr = devm_ioremap_resource(&pdev->dev, res0); > + if (IS_ERR(ctlr->sctrl_addr)) { > + ctlr->sctrl_addr = NULL; > + return -ENOMEM; > + } > + > + return 0; > +} > + > +static int hisi_i2c_recovery_init(struct hisi_i2c_controller *ctlr) > +{ > + struct platform_device *pdev = to_platform_device(ctlr->dev); > + struct i2c_adapter *adapter = &ctlr->adapter; > + int ret; > + > + if (acpi_disabled) > + return -ENODEV; > + > + ret = hisi_i2c_get_bus_recovery_res(ctlr, pdev); > + if (ret) > + return ret; > + > + ctlr->rinfo = (struct i2c_bus_recovery_info) { > + .get_scl = hisi_i2c_recovery_get_scl, > + .get_sda = hisi_i2c_recovery_get_sda, > + .set_scl = hisi_i2c_recovery_set_scl, > + .prepare_recovery = hisi_i2c_prepare_recovery, > + .unprepare_recovery = hisi_i2c_unprepare_recovery, > + .recover_bus = i2c_generic_scl_recovery, > + }; > + adapter->bus_recovery_info = &ctlr->rinfo; > + ctlr->acpi_handle = ACPI_HANDLE(ctlr->dev); > + > + return 0; > +} > +#else > +static int hisi_i2c_recovery_init(struct hisi_i2c_controller *ctlr) { return -ENODEV; } > +#endif /* CONFIG_ACPI */ > + > static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) > { > struct i2c_msg *msg = ctlr->msgs; > @@ -496,6 +638,10 @@ static int hisi_i2c_probe(struct platform_device *pdev) > > hisi_i2c_configure_bus(ctlr); > > + ret = hisi_i2c_recovery_init(ctlr); > + if (ret) > + dev_info(ctlr->dev, "I2C bus recovery not available\n"); > + > adapter = &ctlr->adapter; > snprintf(adapter->name, sizeof(adapter->name), > "HiSilicon I2C Controller %s", dev_name(dev));