From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751408AbdJCXDY (ORCPT ); Tue, 3 Oct 2017 19:03:24 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:53839 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751090AbdJCXDV (ORCPT ); Tue, 3 Oct 2017 19:03:21 -0400 X-Google-Smtp-Source: AOwi7QBXGNTz/lzRYiInMDg9gtHHfUEIdudhIgmVSpuV0IjdJgtNt4nFWCRZtqFBh4sBdFrqpC9LtQ== From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/4] Tegra DMA clocks addition / correction Date: Wed, 4 Oct 2017 02:02:37 +0300 Message-Id: X-Mailer: git-send-email 2.14.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchset is factored out from the AHB DMA driver 'introduction' series as per drivers/dma/ subsystem maintainer request. Change log: v2: - Added patch that corrects parent of the APB DMA clock gate in the 'common' clock gate definition. - Added patch that makes Tegra20 to utilize the 'common' APB DMA clock gate definition. Dmitry Osipenko (4): clk: tegra: Add AHB DMA clock entry clk: tegra: Correct parent of the APBDMA clock clk: tegra20: Use common definition of APBDMA clock gate clk: tegra20: Bump SCLK clock rate to 216MHz drivers/clk/tegra/clk-id.h | 1 + drivers/clk/tegra/clk-tegra-periph.c | 3 ++- drivers/clk/tegra/clk-tegra20.c | 9 +++------ drivers/clk/tegra/clk-tegra30.c | 1 + 4 files changed, 7 insertions(+), 7 deletions(-) -- 2.14.1