From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88F5EC77B75 for ; Mon, 8 May 2023 16:05:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233321AbjEHQFk (ORCPT ); Mon, 8 May 2023 12:05:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232528AbjEHQF3 (ORCPT ); Mon, 8 May 2023 12:05:29 -0400 Received: from michel.telenet-ops.be (michel.telenet-ops.be [IPv6:2a02:1800:110:4::f00:18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3734555B6 for ; Mon, 8 May 2023 09:05:28 -0700 (PDT) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed30:6a18:41e7:fcfe:24c0]) by michel.telenet-ops.be with bizsmtp id uG5R290062WBekD06G5Rm7; Mon, 08 May 2023 18:05:25 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1pw3MU-001XSk-9e; Mon, 08 May 2023 18:05:25 +0200 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1pw3Ma-00BTF8-WB; Mon, 08 May 2023 18:05:25 +0200 From: Geert Uytterhoeven To: Marc Zyngier , Russell King , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 0/2] ARM/arm64: Mark all accessor functions inline Date: Mon, 8 May 2023 18:05:17 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, This patch series adds missing "inline" keywords to the few perf accessors that lack them. BTW, I tried converting my local timing code to the new unified system. This works fine on arm64, but broke on arm32. Is read_pmccntr() supposed to work on arm32? I get an undefined instruction exception on Cortex A15 and A9. Before, my custom code used "mrc p15, 0, %0, c9, c13, 0" (as is also used in arch/arm/kernel/perf_event_v7.c), for which there is no accessor yet. Thanks for your comments! Geert Uytterhoeven (2): ARM: perf: Mark all accessor functions inline arm64: perf: Mark all accessor functions inline arch/arm/include/asm/arm_pmuv3.h | 6 +++--- arch/arm64/include/asm/arm_pmuv3.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) -- 2.34.1 Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds