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Thu, 29 Jan 2026 02:16:50 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:5792:2065:403:a80b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066be77b5sm178642065e9.2.2026.01.29.02.16.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 02:16:50 -0800 (PST) From: Biju X-Google-Original-From: Biju To: biju.das.au@gmail.com Cc: linux-renesas-soc@vger.kernel.org, biju.das.jz@bp.renesas.com, Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Michael Turquette , Stephen Boyd , Lad Prabhakar , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH RESEND 0/9] Add Renesas RZ/G3L PINCONTROL support Date: Thu, 29 Jan 2026 10:16:35 +0000 Message-ID: X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Biju Das Hi All, This patch series aims to add basic pincontrol support for RZ/G3L SoC. The RZ/G3L pinctrl has OTHER_POC register compared to other SoCs for setting IO domain volage for AWO, ISO and WDT. Document the reset-names as all SOCs has multiple resets. Document the bindings for RZ/G3L SOC and add pinctrl definitions in driver. Add pincontrol device node and add pincontrol support for SCIF0 and GBETH nodes. Note: Some IPs needs to set the register IPCONT_SEL_CLONECH in SYSC to control the clone channel of the IP. Plan to add clone channel control support later. The IP's involing clone channel needs to do the setup as per the below flow (1) Set SYS_IPCONT_SEL_CLONECH register as necessary (2) Set the PWPR register to allow writing to the PFC_m register. After setting the PWPR.B0WI bit to “0” (initial value = 1), set the PWPR.PFCWE bit to “1” (initial value = 0). Select the required function from Functions 0-15. (Hereafter, Function1 setting example) (3) Set PFC_m = 0001b and switch to Function1. (4) Set the PMC_m register to “1” (initial value = 0). (5) Set the PFC_m register to write-protected. After setting the PWPR.PFCWE bit to “0”, set the PWPR.B0WI bit to “1”. The clock and dtsi/dts patches depend upon [1] [1] https://lore.kernel.org/all/20260128125850.425264-1-biju.das.jz@bp.renesas.com/ Biju Das (9): dt-bindings: pinctrl: renesas: Document reset-names dt-bindings: pinctrl: renesas: Document RZ/G3L SoC clk: renesas: r9a08g046: Add GPIO clocks/resets pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO} pinctrl: renesas: rzg2l: Add OEN support for RZ/G3L pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC arm64: dts: renesas: r9a08g046: Add pincontrol node arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface .../pinctrl/renesas,rzg2l-pinctrl.yaml | 16 + arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 10 + .../boot/dts/renesas/r9a08g046l48-smarc.dts | 13 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 1 + .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 92 ++++++ drivers/clk/renesas/r9a08g046-cpg.c | 6 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 285 +++++++++++++++++- .../pinctrl/renesas,r9a08g046-pinctrl.h | 39 +++ 14 files changed, 465 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h -- 2.43.0