From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-43103.protonmail.ch (mail-43103.protonmail.ch [185.70.43.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A1C726C3B0 for ; Fri, 27 Mar 2026 15:10:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.103 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774624250; cv=none; b=lyJDFcK4vtgztU2PJgaRLqVC4gvmZeamHPguUVsvgw3inwshaLWZiHAav98O05hJtM5Uw9/maP5VSIZox3JH14GftqBMtEN02zHuEyI/Ys2VZgQThJOVYAFmmJCCWTZJ7ydDvXVMUOif0qOa5caKkNUVCld2txtXoxEoeH6Wc0c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774624250; c=relaxed/simple; bh=olMb0Z2S8rbH/uBKtreKAOebVGufXccH4d/mS2n9QaU=; h=Date:To:From:Cc:Subject:Message-ID:MIME-Version:Content-Type; b=lbA+wnQDPmr+Fqm5pSvUvjTAjonCF3bpIISCgdAZBHwovPtcgQmcurXjq4lL6OKWB5OboYOrOciyygvBTSDQSdrlPTOPUBCOcOt1pu4bmE8xArAiusYHvHLdGqGsHQRlxkK+gI9U8BnWHW8BCJ8dH4KlcUKHGNjIdbnYHrn3Gcw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=SawrIhqB; arc=none smtp.client-ip=185.70.43.103 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="SawrIhqB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1774624245; x=1774883445; bh=RcQj4EbZzZ1+dvBH7OfwGphs9SvFUct5DjBtGBZPa94=; h=Date:To:From:Cc:Subject:Message-ID:Feedback-ID:From:To:Cc:Date: Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=SawrIhqBWWlwTqHCLr/xnfg0kSPyd4TIZuqSoHlT+tqHjKop8rf2JKCsDP8/6Edtb YmQrN6gp0BZFC0KQ5/6EB/djLrBKSVoKzQwB04GMAB9ZTO1Dtsi4f/hZcBHFQXhokk 1qLcHr15voKebtp5zU/xI7/MirhUFDnn20EkpN7nFNmwHhtB/V6jW7rrcKYh7N3bdU OV4gIzO1dCczfSFc8R6OKeByBfVlFkHGsBElHYDVzSQjr//HLJ4QY+/ZH9R6YXBDrg EsYcTHEanFxYsjt94AlmuH2cu37zYka417CMrp9SGHQ7QnboiCI3LJbhMhbT3p6J5t dJVTxp65OfaAA== Date: Fri, 27 Mar 2026 15:10:39 +0000 To: bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, xin@zytor.com, chang.seok.bae@intel.com, mingo@redhat.com, elena.reshetova@intel.com, maciej.wieczor-retman@intel.com, babu.moger@amd.com, sohil.mehta@intel.com, pawan.kumar.gupta@linux.intel.com, pmladek@suse.com, nik.borisov@suse.com, ptesarik@suse.com, darwi@linutronix.de, tglx@kernel.org, peterz@infradead.org, jpoimboe@kernel.org, ak@linux.intel.com From: Maciej Wieczor-Retman Cc: linux-kernel@vger.kernel.org, x86@kernel.org, m.wieczorretman@pm.me Subject: [PATCH v12 0/4] x86: Capability bits fix and required bits sanity check Message-ID: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: cd956a0320711d9c1ceba2c89a31afe133d6d42d Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Series aims to fix the inconsistency between the cpuinfo behavior and the documentation. Specifically the features that are not compiled are still present in the cpuinfo bitmasks as enabled. This is not in line with the documentation which specifies that not-compiled features are not present in /proc/cpuinfo. Along adding the disabled feature bitmask initializer array, the complementary required bitmask initializer is also added. It can be used to provide a sanity check, after the cpu identification is finished, to make sure every required bit is set in the final bitmask. A warning with the cpu number and all required bits that were not set is emitted in case of the sanity check failure. Before adding the sanity check a small cleanup can be done. Three places open code an operation that retrieves either a feature string or, if the string is not present, the feature number in word:bit format. One of these places also doesn't check whether the string is actually there or not. While currently not a problem (all the features in the checked list have corresponding strings) it may cause a failure if more entries are added. The cleanup patch fixes that and simplifies the other two instances. Patches are based on v7.0-rc5 Previous patchset versions: v11: https://lore.kernel.org/all/cover.1774008873.git.m.wieczorretman@pm.me= / v10: https://lore.kernel.org/all/cover.1773771353.git.m.wieczorretman@pm.me= / v9: https://lore.kernel.org/all/cover.1773165421.git.m.wieczorretman@pm.me= / v8: https://lore.kernel.org/all/cover.1772453012.git.m.wieczorretman@pm.me= / v7: https://lore.kernel.org/all/cover.1771936214.git.m.wieczorretman@pm.me= / v6: https://lore.kernel.org/all/cover.1771590895.git.m.wieczorretman@pm.me= / v5: https://lore.kernel.org/all/cover.1770908783.git.m.wieczorretman@pm.me= / v4: https://lore.kernel.org/all/20250724125346.2792543-1-maciej.wieczor-re= tman@intel.com/ v3: https://lore.kernel.org/all/20250724094554.2153919-1-maciej.wieczor-re= tman@intel.com/ v2: https://lore.kernel.org/all/20250723092250.3411923-1-maciej.wieczor-re= tman@intel.com/ v1: https://lore.kernel.org/all/20250722074439.4069992-1-maciej.wieczor-re= tman@intel.com/ Maciej Wieczor-Retman (4): x86/cpu: Clear feature bits disabled at compile-time x86/cpu: Check if feature string is non-zero x86/cpu: Do a sanity check on required feature bits x86/cpu: Clear feature bits whose dependencies were cleared arch/x86/include/asm/cpufeature.h | 1 + arch/x86/kernel/cpu/common.c | 63 +++++++++++++++++++++++++++--- arch/x86/kernel/cpu/cpu.h | 4 ++ arch/x86/kernel/cpu/cpuid-deps.c | 21 +++++----- arch/x86/tools/cpufeaturemasks.awk | 6 +++ 5 files changed, 79 insertions(+), 16 deletions(-) --=20 2.53.0