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This series hardens s10_ops_write() and s10_ops_write_complete() so those paths cannot skip a completion wait, treat BUFFER_DONE | ERROR as success, or return immediately when the DT-supplied config_complete_timeout_us is left at 0. No dependency on the stratix10-svc accumulate changes. 1) always wait for svc buffer completion s10_ops_write() skips wait_for_completion_timeout() when priv->status is already set. That skip is unnecessary and unsafe: the callback may fire between the CLAIM/SUBMIT send and the wait check. Always call the wait; if complete() already ran, the done counter is raised and the wait returns immediately. 2) prefer ERROR over BUFFER_DONE BUFFER_DONE is checked before ERROR, so a combined BUFFER_DONE | ERROR status is treated as success. Check ERROR first so that status aborts the write. Also clear priv->status at the start of write_init so stale bits from an aborted transfer cannot leak into the next reconfiguration. 3) floor config_complete_timeout_us of-fpga-region leaves config_complete_timeout_us at 0 when the DT property is absent. usecs_to_jiffies(0) makes write_complete return immediately, while reconfiguration takes ~600ms in practice. Enforce S10_RECONFIG_TIMEOUT as a minimum floor while still honouring any larger caller-supplied value. Note this prevents a DT property from lowering the timeout below that floor. Adrian Ng Ho Yin (3): fpga: stratix10-soc: always wait for svc buffer completion fpga: stratix10-soc: prefer ERROR over BUFFER_DONE fpga: stratix10-soc: floor config_complete_timeout_us drivers/fpga/stratix10-soc.c | 41 ++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 14 deletions(-) -- 2.49.GIT