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Mon, 2 Nov 2026 19:49:56 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Mon, 2 Nov 2026 19:49:55 -0800 From: Nicolin Chen To: Jason Gunthorpe , , Will Deacon , Robin Murphy , Catalin Marinas , , Danilo Krummrich , Johan Hovold , Marek Szyprowski CC: Mark Rutland , Greg Kroah-Hartman , Pranjal Shrivastava , "Mostafa Saleh" , , , , Sonang Patel , Ankit Agrawal , Subject: [PATCH v2 0/7] iommu/arm-smmu-v3: Support guest-level Realm VSMMU (Part-1) Date: Mon, 2 Nov 2026 19:49:43 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055DA:EE_|IA1PR12MB6017:EE_ X-MS-Office365-Filtering-Correlation-Id: 0021aba5-4385-4a33-1dce-08df395d8e07 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700016|82310400026|376014|1800799024|23010399003|6133799003|10067099003|261102123227099003|20052099010|18002099003|3023799007|13003099007|56012099006|261021135927099003|5023799004|11063799006|261022075727099003|261026121527099003|261021121427099003|261026140227099003|261022105027099003|261028144727099003|261009223027099003|261021123027099003|260925022911599003|260925021311599003|260925021911599003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qgK2iaz9CfhBsrSL+XAdxuaI6fYb/zIE1Mk+ZoAMaZ8Ne3MRC1CAiw+ilx6gV2AQjIvZZwouAgcV5N6KoPZ3UCnoOdWXeJRHWEO1tDPmQV3DZ7Q4WbKhW16zkQ4zsFJhNuTB4ux9s/11GPwrB/hTTLZy5L1oWQFUxxiwUP8KzFtYzbgdo6OIyczS7eEtk84HOFG8ZeE+f8xrgnpv6FWE9qb7C4+IOS/WOtkbs1jTT1JHcoh0o+uG4Jum5kGYOij/KHypX10NoWSMyZJ3RAsLUiJ7EPjooBDJFCOTvQWEhwgAArqHvJOb68E4c/8LldnvgwQj6veONx6aBNHG7N1NGM6kxI7vkI1P5rBbmnNl0VTs8XA+dqj5dT+zuxDyOiPAHTb/QMvnGYEddxRS09XwffMSCvGD1rW7RqwCLNDNVh7wONCA9u/TjjR2ngkRym64 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2026 03:50:08.5779 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0021aba5-4385-4a33-1dce-08df395d8e07 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6017 This series prepares Realm guest IOMMU and DMA subsystems for devices that are present but not yet inside the Realm trust boundary. Inside a confidential guest, we expect that all the iommus are going to be T=1 aware; there seems to be no interest in supporting IOMMUs that handle T=0 only. This means they only work on devices that have been put into the run state and issue T=1 transactions. Today an iommu driver assumes it translates for every device behind it: it probes the device, takes a translating default domain, and puts the DMA API on its page tables. That assumption is wrong for T=0 devices, whose DMA the hypervisor translates instead, so the mappings made by the guest are never consulted and the device silently stops working. To solve this problem, make TDISP T=0 the default for devices associated with a confidential IOMMU. The tdisp_t1 flag records the future T=1 state. While T=0, the device remains outside the Realm trust boundary. Its DMA is translated by the host or hypervisor: [device: T=0] ===> [hypervisor] ===> [memory] | +-- (guest association) --> [confidential IOMMU: blocking DMA] Legend: ===> DMA path; --> guest topology and control After reaching T=1, the device is inside the Realm trust boundary. Its DMA may use the guest VSMMU after RMM binds the device to its virtual stream: [device] ===> [VSMMU: S1] ===> [RMM/PSMMU: S2 + DPT] ===> [memory] As part 1 of Realm VSMMU support, implement enough core infrastructure to manage a confidential vIOMMU: - Detect and mark it as confidential in the core iommu structures - Support devices in T=0 mode by keeping the DMA API in direct mode. The iommu is up and running, but parks such a device in its blocking domain and translates for nothing, as the core takes over what the device still needs, which today is ATS - Keep it parked: refuse a translating domain by every route in, whether through the default domain, sysfs, group attach or replace, or PASID Part 1 only adds the helpers required for T=0 setup and teardown. It does not add iommu_tdisp_enter_t1() until part 2 has a transition to perform. Then implement SMMUv3 support: - Let a CPU-integrated IOMMU declare that its DMA can reach private memory, so coherent allocations and streaming mappings avoid the SWIOTLB shared pool - Identify a T=1 VSMMU using trusted RSI because firmware does not distinguish it from a normal T=0 SMMU - Validate the firmware MMIO range against RSI before activating the VSMMU and allocating its queues and tables from private memory The series is on github: https://github.com/nicolinc/iommufd/commits/smmuv3_realm_guest_p1-v2 Changelog v2: * Rebase on v7.4-rc1 * Drop Assisted-by tags * Drop Aneesh's firmware patch that was merged * Skip Tegra CMDQV implementation in the realm world * Use arm_smccc_1_2_smc() to zero inputs as RMM spec demands * Add missing iommu_using_t0_stream() check in iommu_dma_prepare_msi() v1: https://lore.kernel.org/all/cover.1789010941.git.nicolinc@nvidia.com/ Future work =========== Part 2 will add the T=1 transition after validation through: - TSM, whose guest-side interface remains under discussion - RMM, using the Arm-specific RSI VDEV command For a multi-device IOMMU group, the first device accepted into T=1 claims the group. Part 2 will reject T=1 for every other member. The current RSI binding validation returns one VSID, so part 2 must reject a firmware specification containing multiple SIDs upon the T=1 transition. Nicolin Chen (7): firmware: arm_rmm: Add VSMMU commands and fields dma-mapping: Let a device declare that it reaches private memory dma-mapping: Keep DMA memory private for capable devices iommu: Let a driver mark an IOMMU as confidential iommu: Introduce TDISP T=0 state for confidential IOMMUs iommu: Park TDISP T=0 devices in the blocking domain iommu/arm-smmu-v3: Probe a guest-level Realm VSMMU via RSI commands drivers/iommu/Makefile | 3 + drivers/iommu/iommu-priv.h | 19 +++++ include/linux/arm-rsi-cmds.h | 29 +++++++ include/linux/arm-smccc-rsi.h | 20 +++++ include/linux/device.h | 4 + include/linux/dma-direct.h | 7 +- include/linux/dma-mapping.h | 4 + include/linux/iommu.h | 14 ++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 64 ++++++++++++++- drivers/iommu/iommu-cc.c | 57 +++++++++++++ drivers/iommu/iommu.c | 91 +++++++++++++++++++-- kernel/dma/direct.c | 16 ++-- kernel/dma/mapping.c | 23 +++++- kernel/dma/swiotlb.c | 2 +- 14 files changed, 335 insertions(+), 18 deletions(-) create mode 100644 drivers/iommu/iommu-cc.c base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 -- 2.43.0