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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sXgS1+lDEEbtCJnlvzsC/ht3uPMAhDbkBeQVGdhHsgkzBLTp4JKQE6tt/ss0yRNzGFZ51hutx4ShLfKMqfkWVRWY2gl6JZehLDBB64izDQoCfWV3Dn+0Vf7quJsqBjb9fUWZkUHpF6/Xi1aevHDMBtvgGDwJZAm/E3jgdaL+oxgmQriHtcFrgYW1rTi1+HxHTbI7iUKSOixla75mIwoAb0P/Bg0efJfHP5KY24QJLq7jElGlCzYz3q0Hrzb9R9KID5C2NA1oGWVz23vOUwC/a0+G6OfUoLkKYWunjzEsbLUjCDhwJijsgDE96J9bu++D6LneuxU5vQkQy0bPnvw/ieh2RfFYDDpbIq5e+hXAsQqpTk0BeFrkPbXtXxZEU0CD426J0Tdex9nXm3o72t32OwXMweBbQCmrfAs3nqPLv9X+pL0sHDQUYM6GivKMvZaC X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2026 18:34:17.4438 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83981f65-0ed1-4ed3-75f1-08df39d9119d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL2PEPF000352D5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5916 This series is split from a bigger SMMUv3 series, so that the PCI and the IOMMU core changes can be reviewed and merged on their own: https://lore.kernel.org/all/cover.1790188510.git.nicolinc@nvidia.com/ The SMMUv3 ATC invalidation timeout handling in that series will depend on this series. pci_dev_reset_iommu_prepare() blocks the IOMMU translation and ATS of a PCI device before a reset. pci_dev_reset_iommu_done() restores them after the reset. However, done() is called unconditionally, even when the reset has failed. A failed reset gives no guarantee that the device cache is clean. For an ATS-capable device, its ATC might still have stale entries pointing to the memory pages that the OS has reclaimed. Re-attaching such a device to its translation domains could corrupt the system memory. Thus, pass in the reset result to pci_dev_reset_iommu_done(). On a failure, keep the device blocked until a subsequent reset succeeds. This new policy applies to every ATS-capable PCI device behind an IOMMU, so no IOMMU driver needs to opt in. First, fix two PCI reset issues found along the way. A probe of the reset capability must not block the IOMMU, as it is only a state query. And the cxl_reset_bus_function() must not report a "cxl_bus" method that can never succeed. Then, convert gdev->blocked from a bool into an enum in the IOMMU core, so that a failed reset can be told apart from an ongoing reset. Also, pass the blocked state of a device being removed into iommu_deinit_device(), which lets the release_domain get the correct old domain. Note that the PCI reset functions do overload -ENOTTY. It might mean either "the reset was not attempted" or "this method failed, so try the next one". The IOMMU core cannot tell these two apart. So, it keeps the device blocked on -ENOTTY as well, with a FIXME and a warning. This is on Github: https://github.com/nicolinc/iommufd/commits/iommu_reset_failure-v1 Changelog v1: * Drop the Assisted-by tags * Split from the SMMUv3 series above * Carry over the Reviewed-by tags from Baolu and Jason Nicolin Chen (5): PCI: Don't suspend IOMMU when probing reset capability PCI/CXL: Probe the underlying bus reset in cxl_reset_bus_function() iommu: Convert gdev->blocked from bool to enum blocked_reason iommu: Pass in gdev's blocked state to iommu_deinit_device() iommu: Pass in reset result to pci_dev_reset_iommu_done() include/linux/iommu.h | 5 ++- drivers/iommu/iommu.c | 87 ++++++++++++++++++++++++++++++++++++------ drivers/pci/pci-acpi.c | 2 +- drivers/pci/pci.c | 37 +++++++++++------- drivers/pci/quirks.c | 13 ++++--- 5 files changed, 111 insertions(+), 33 deletions(-) base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 -- 2.43.0