From: Jiaxing Hu <gahing@gahingwoo.com>
To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org,
will@kernel.org, robin.murphy@arm.com, p.zabel@pengutronix.de,
ogabbay@kernel.org, zhangqing@rock-chips.com
Cc: royalnet026@gmail.com, ulf.hansson@oss.qualcomm.com,
abel.vesa@oss.qualcomm.com, sebastian.reichel@collabora.com,
sidong.yang@furiosa.ai, u.kleine-koenig@baylibre.com,
chaoyi.chen@rock-chips.com, shawn.lin@rock-chips.com,
finley.xiao@rock-chips.com, diederik@cknow-tech.com,
alchark@flipper.net, leonard@lausen.nl, vlwwwwww@gmail.com,
jeff.hugo@oss.qualcomm.com, rfoss@kernel.org,
dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org, iommu@lists.linux.dev,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v17 00/12] accel/rocket: RK3576 NPU (RKNN) enablement
Date: Sat, 14 Nov 2026 16:05:17 +1300 [thread overview]
Message-ID: <cover.1794615324.git.gahing@gahingwoo.com> (raw)
This series adds RK3576 NPU (RKNN) support to the mainline DRM rocket
driver.
Based on: next-20261113
The pmdomain part of v16 9/16 is now a separate series on Ulf's next
(v16 10/16 is dropped). 12/12 needs its 2/3 to make the NPU domain take
its supply:
https://lore.kernel.org/all/cover.1794615323.git.gahing@gahingwoo.com/
Changes in v17:
- Dropped v16 7/16, 10/16 and 14/16 (the power-domain reset and the
extra domain clocks), following Finley Xiao's (Rockchip) review.
- Following Heiko, the clock indices are now ROCKET_CLK_* constants
(1/12 and 9/12).
- The pmdomain changes are now a separate series, linked above.
Testing:
Tested on a Radxa ROCK 4D running Armbian edge 7.3, with the v17
changes backported (this series and the pmdomain series):
- charsiu (https://github.com/gahingwoo/charsiu), an open source LLM
runtime that drives the NPU through the rocket UAPI (/dev/accel)
without Mesa or the vendor runtime, ran Qwen3-0.6B (Q4_0) 30 times
after a warm reboot and 30 times after a cold power-on. Each run starts
with the NPU power domain off. All 60 outputs are identical, with no
job timeout, IOMMU error or SError.
- Job timeouts forced with a 1 ms timeout, three times in one boot:
after each, the next run gives the same output as before, with no
error.
The v15/v16 comparison of the reset order is in 4/12.
Logs: https://github.com/gahingwoo/linux-rk3576-npu/tree/main/board-logs
Known issue: in v16 I saw the IOMMU not recover after repeated resets
with a 2 ms job timeout ("MMU_DTE_ADDR is not functioning"). With v17,
after three rounds of forced timeouts in one boot, it recovered each
time; I have not looked into what changed.
Tool use:
An LLM helped me read code and technical material and write part of the
implementation. Some of the code in the series was first drafted by an
LLM, and the commit messages and cover letters of earlier versions were
mostly written by an LLM.
I reviewed the generated code and tested the changes on real hardware.
I also used an LLM to write test scripts and to compare register write
traces.
For v17 I wrote the cover letter, commit messages and code comments
myself in Chinese first and translated them into English with an LLM.
Tag changes:
- 1/12 changed in v17. Heiko, does your Reviewed-by still apply? If the
change goes beyond what you reviewed, please take another look.
- 7/12 keeps Conor's Acked-by. The clock count changed from five to four
in v16; Conor, please confirm it still applies.
- Tomeu, the GET_PARAM enum in 10/12 is unchanged (RK3588 = 1,
RK3576 = 2). Is that fine?
Igor Paunovic (1):
accel/rocket: request the core clocks by name
Jiaxing Hu (11):
accel/rocket: take the completion register writes under job_lock
accel/rocket: wait for a running IRQ handler before resetting a core
accel/rocket: let the core suspend after a reset
accel/rocket: factor the completion tail out of the IRQ handler
dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core
dt-bindings: iommu: rockchip: describe the RK3576 NPU MMU
accel/rocket: select the per-core clock and reset counts from match
data
accel/rocket: add RK3576 NPU (RKNN) support
accel/rocket: add a GET_PARAM ioctl for the hardware version
arm64: dts: rockchip: add NPU (RKNN) nodes to rk3576
arm64: dts: rockchip: enable the NPU on rk3576-rock-4d
.../bindings/iommu/rockchip,iommu.yaml | 26 ++++++
.../npu/rockchip,rk3588-rknn-core.yaml | 40 ++++++++-
.../boot/dts/rockchip/rk3576-rock-4d.dts | 22 +++++
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 70 +++++++++++++++-
drivers/accel/rocket/rocket_core.c | 14 +++-
drivers/accel/rocket/rocket_core.h | 20 ++++-
drivers/accel/rocket/rocket_device.c | 3 +-
drivers/accel/rocket/rocket_drv.c | 61 ++++++++++++--
drivers/accel/rocket/rocket_drv.h | 2 +
drivers/accel/rocket/rocket_job.c | 84 ++++++++++++++-----
include/uapi/drm/rocket_accel.h | 40 +++++++++
11 files changed, 345 insertions(+), 37 deletions(-)
base-commit: 84abb955b1015477aa11a96e2f3ac1b938b77f48
--
2.43.0
next reply other threads:[~2026-11-14 3:05 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-14 3:05 Jiaxing Hu [this message]
2026-11-14 3:05 ` [PATCH v17 01/12] accel/rocket: request the core clocks by name Jiaxing Hu
2026-11-14 3:05 ` [PATCH v17 02/12] accel/rocket: take the completion register writes under job_lock Jiaxing Hu
2026-11-14 3:05 ` [PATCH v17 03/12] accel/rocket: wait for a running IRQ handler before resetting a core Jiaxing Hu
2026-11-14 3:05 ` [PATCH v17 04/12] accel/rocket: let the core suspend after a reset Jiaxing Hu
2026-11-14 3:05 ` [PATCH v17 05/12] accel/rocket: factor the completion tail out of the IRQ handler Jiaxing Hu
2026-11-14 3:05 ` [PATCH v17 06/12] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Jiaxing Hu
2026-11-14 3:05 ` [PATCH v17 07/12] dt-bindings: iommu: rockchip: describe the RK3576 NPU MMU Jiaxing Hu
2026-11-14 3:05 ` [PATCH v17 08/12] accel/rocket: select the per-core clock and reset counts from match data Jiaxing Hu
2026-11-14 3:05 ` [PATCH v17 09/12] accel/rocket: add RK3576 NPU (RKNN) support Jiaxing Hu
2026-11-14 3:05 ` [PATCH v17 10/12] accel/rocket: add a GET_PARAM ioctl for the hardware version Jiaxing Hu
2026-11-14 3:05 ` [PATCH v17 11/12] arm64: dts: rockchip: add NPU (RKNN) nodes to rk3576 Jiaxing Hu
2026-11-14 3:05 ` [PATCH v17 12/12] arm64: dts: rockchip: enable the NPU on rk3576-rock-4d Jiaxing Hu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cover.1794615324.git.gahing@gahingwoo.com \
--to=gahing@gahingwoo.com \
--cc=abel.vesa@oss.qualcomm.com \
--cc=alchark@flipper.net \
--cc=chaoyi.chen@rock-chips.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=diederik@cknow-tech.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=finley.xiao@rock-chips.com \
--cc=heiko@sntech.de \
--cc=iommu@lists.linux.dev \
--cc=jeff.hugo@oss.qualcomm.com \
--cc=joro@8bytes.org \
--cc=krzk+dt@kernel.org \
--cc=leonard@lausen.nl \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=ogabbay@kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=rfoss@kernel.org \
--cc=robh@kernel.org \
--cc=robin.murphy@arm.com \
--cc=royalnet026@gmail.com \
--cc=sebastian.reichel@collabora.com \
--cc=shawn.lin@rock-chips.com \
--cc=sidong.yang@furiosa.ai \
--cc=tomeu@tomeuvizoso.net \
--cc=u.kleine-koenig@baylibre.com \
--cc=ulf.hansson@oss.qualcomm.com \
--cc=vlwwwwww@gmail.com \
--cc=will@kernel.org \
--cc=zhangqing@rock-chips.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®