From: Len Brown <lenb@kernel.org>
To: rjw@rjwysocki.net, linux-pm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, Len Brown <len.brown@intel.com>
Subject: [PATCH 1/5] x86: msr-index.h: define EPB mid-points
Date: Thu, 11 May 2017 22:00:19 -0400 [thread overview]
Message-ID: <d0117a0e2780f7803fe55d543ab119416d7582e6.1494552477.git.len.brown@intel.com> (raw)
In-Reply-To: <20170512020023.23204-1-lenb@kernel.org>
From: Len Brown <len.brown@intel.com>
These are currently open-coded into intel_pstate.c
Signed-off-by: Len Brown <len.brown@intel.com>
---
arch/x86/include/asm/msr-index.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 710273c617b8..a92d9bd154f6 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -462,9 +462,11 @@
#define MSR_MISC_PWR_MGMT 0x000001aa
#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
-#define ENERGY_PERF_BIAS_PERFORMANCE 0
-#define ENERGY_PERF_BIAS_NORMAL 6
-#define ENERGY_PERF_BIAS_POWERSAVE 15
+#define ENERGY_PERF_BIAS_PERFORMANCE 0
+#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
+#define ENERGY_PERF_BIAS_NORMAL 6
+#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
+#define ENERGY_PERF_BIAS_POWERSAVE 15
#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
--
2.11.0.161.g6610af872
next prev parent reply other threads:[~2017-05-12 2:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-12 2:00 [GIT PULL] power utilities update Len Brown
2017-05-12 2:00 ` Len Brown [this message]
2017-05-12 2:00 ` [PATCH 2/5] x86: msr-index.h: define HWP.EPP values Len Brown
2017-05-12 2:00 ` [PATCH 3/5] x86: msr-index.h: fix shifts to ULL results in HWP macros Len Brown
2017-05-12 2:00 ` [PATCH 4/5] tools/power x86_energy_perf_policy: support HWP.EPP Len Brown
2017-05-12 2:00 ` [PATCH 5/5] intel_pstate: use updated msr-index.h HWP.EPP values Len Brown
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