From: Daniel Golle <daniel@makrotopia.org>
To: Hauke Mehrtens <hauke@hauke-m.de>, Andrew Lunn <andrew@lunn.ch>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Russell King <linux@armlinux.org.uk>,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org
Cc: Andreas Schirm <andreas.schirm@siemens.com>,
Lukas Stockmann <lukas.stockmann@siemens.com>,
Alexander Sverdlin <alexander.sverdlin@siemens.com>,
Peter Christen <peter.christen@siemens.com>,
Avinash Jayaraman <ajayaraman@maxlinear.com>,
Bing tao Xu <bxu@maxlinear.com>, Liang Xu <lxu@maxlinear.com>,
Juraj Povazanec <jpovazanec@maxlinear.com>,
"Fanni (Fang-Yi) Chan" <fchan@maxlinear.com>,
"Benny (Ying-Tsan) Weng" <yweng@maxlinear.com>,
"Livia M. Rosu" <lrosu@maxlinear.com>,
John Crispin <john@phrozen.org>
Subject: [PATCH net-next 4/6] net: dsa: lantiq_gswip: support offset of MII registers
Date: Tue, 26 Aug 2025 01:14:16 +0100 [thread overview]
Message-ID: <d01cb83b94814f73669c2ca348b1424bce90588f.1756163848.git.daniel@makrotopia.org> (raw)
In-Reply-To: <cover.1756163848.git.daniel@makrotopia.org>
The MaxLinear GSW1xx family got a single (R)(G)MII port at index 5 but
the registers MII_PCDU and MII_CFG are those of port 0.
Allow applying an offset for the port index to access those registers.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/dsa/lantiq_gswip.c | 12 ++++++++++--
drivers/net/dsa/lantiq_gswip.h | 1 +
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c
index 7ffaa6481271..f9b03fb5f57b 100644
--- a/drivers/net/dsa/lantiq_gswip.c
+++ b/drivers/net/dsa/lantiq_gswip.c
@@ -183,21 +183,29 @@ static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
int port)
{
+ int reg_port;
+
/* MII_CFG register only exists for MII ports */
if (!(priv->hw_info->mii_ports & BIT(port)))
return;
- gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
+ reg_port = port + priv->hw_info->mii_port_reg_offset;
+
+ gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(reg_port));
}
static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
int port)
{
+ int reg_port;
+
/* MII_PCDU register only exists for MII ports */
if (!(priv->hw_info->mii_ports & BIT(port)))
return;
- switch (port) {
+ reg_port = port + priv->hw_info->mii_port_reg_offset;
+
+ switch (reg_port) {
case 0:
gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
break;
diff --git a/drivers/net/dsa/lantiq_gswip.h b/drivers/net/dsa/lantiq_gswip.h
index 19bbe6fddf04..2df9c8e8cfd0 100644
--- a/drivers/net/dsa/lantiq_gswip.h
+++ b/drivers/net/dsa/lantiq_gswip.h
@@ -233,6 +233,7 @@ struct gswip_hw_info {
int max_ports;
unsigned int allowed_cpu_ports;
unsigned int mii_ports;
+ int mii_port_reg_offset;
const struct gswip_pce_microcode (*pce_microcode)[];
size_t pce_microcode_size;
enum dsa_tag_protocol tag_protocol;
--
2.50.1
next prev parent reply other threads:[~2025-08-26 0:14 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-26 0:11 [PATCH net-next 0/6] net: dsa: lantiq_gswip: prepare for supporting MaxLinear GSW1xx Daniel Golle
2025-08-26 0:12 ` [PATCH net-next 1/6] MAINTAINERS: lantiq_gswip: broaden file pattern Daniel Golle
2025-08-26 1:36 ` Andrew Lunn
2025-08-26 0:12 ` [PATCH net-next 3/6] net: dsa: lantiq_gswip: ignore SerDes modes in phylink_mac_config() Daniel Golle
2025-08-26 0:12 ` [PATCH net-next 2/6] net: dsa: lantiq_gswip: support model-specific mac_select_pcs() Daniel Golle
2025-08-26 19:43 ` kernel test robot
2025-08-26 0:14 ` Daniel Golle [this message]
2025-08-26 0:14 ` [PATCH net-next 5/6] net: dsa: lantiq_gswip: support standard MDIO node name Daniel Golle
2025-08-26 1:38 ` Andrew Lunn
2025-08-26 7:23 ` Sverdlin, Alexander
2025-08-26 0:14 ` [PATCH net-next 6/6] net: dsa: lantiq_gswip: move MDIO bus registration to .setup() Daniel Golle
2025-08-26 1:40 ` Andrew Lunn
2025-08-26 7:30 ` Sverdlin, Alexander
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