From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932672AbdJJSKW (ORCPT ); Tue, 10 Oct 2017 14:10:22 -0400 Received: from mail-qt0-f180.google.com ([209.85.216.180]:52710 "EHLO mail-qt0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932427AbdJJSJp (ORCPT ); Tue, 10 Oct 2017 14:09:45 -0400 X-Google-Smtp-Source: AOwi7QC1Sx6KtrLM0ES2awHIPgokPPTMZzyOXZxqPUKcRsD/NkUkhv4pzF20Jq44gmjLGDFD1PTFjg== Subject: Re: [PATCH] PCI: iproc: Allow allocation of multiple MSIs To: Bodo-Merle Sandor , linux-pci@vger.kernel.org Cc: Sandor Bodo-Merle , Bjorn Helgaas , Ray Jui , Scott Branden , Jon Mason , bcm-kernel-feedback-list@broadcom.com, Shawn Lin , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20171007120851.20230-1-sbodomerle@gmail.com> From: Ray Jui Message-ID: Date: Tue, 10 Oct 2017 11:09:34 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <20171007120851.20230-1-sbodomerle@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Bodo, On 10/7/2017 5:08 AM, Bodo-Merle Sandor wrote: > From: Sandor Bodo-Merle > > Add support for allocating multiple MSIs at the same time, so that the > MSI_FLAG_MULTI_PCI_MSI flag can be added to the msi_domain_info > structure. > > Avoid storing the hwirq in the low 5 bits of the message data, as it is > used by the device. Also fix an endianness problem by using readl(). > > Signed-off-by: Sandor Bodo-Merle > --- > drivers/pci/host/pcie-iproc-msi.c | 19 ++++++++++++------- > 1 file changed, 12 insertions(+), 7 deletions(-) > > diff --git a/drivers/pci/host/pcie-iproc-msi.c b/drivers/pci/host/pcie-iproc-msi.c > index 2d0f535a2f69..990fc906d73d 100644 > --- a/drivers/pci/host/pcie-iproc-msi.c > +++ b/drivers/pci/host/pcie-iproc-msi.c > @@ -179,7 +179,7 @@ static struct irq_chip iproc_msi_irq_chip = { > > static struct msi_domain_info iproc_msi_domain_info = { > .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | > - MSI_FLAG_PCI_MSIX, > + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, > .chip = &iproc_msi_irq_chip, > }; > > @@ -237,7 +237,7 @@ static void iproc_msi_irq_compose_msi_msg(struct irq_data *data, > addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq); > msg->address_lo = lower_32_bits(addr); > msg->address_hi = upper_32_bits(addr); > - msg->data = data->hwirq; > + msg->data = data->hwirq << 5; > } > > static struct irq_chip iproc_msi_bottom_irq_chip = { > @@ -251,7 +251,7 @@ static int iproc_msi_irq_domain_alloc(struct irq_domain *domain, > void *args) > { > struct iproc_msi *msi = domain->host_data; > - int hwirq; > + int hwirq, i; > > mutex_lock(&msi->bitmap_lock); > > @@ -267,10 +267,14 @@ static int iproc_msi_irq_domain_alloc(struct irq_domain *domain, > > mutex_unlock(&msi->bitmap_lock); > > - irq_domain_set_info(domain, virq, hwirq, &iproc_msi_bottom_irq_chip, > - domain->host_data, handle_simple_irq, NULL, NULL); > + for (i = 0; i < nr_irqs; i++) { > + irq_domain_set_info(domain, virq + i, hwirq + i, > + &iproc_msi_bottom_irq_chip, > + domain->host_data, handle_simple_irq, > + NULL, NULL); > + } > > - return 0; > + return hwirq; > } > > static void iproc_msi_irq_domain_free(struct irq_domain *domain, > @@ -302,7 +306,8 @@ static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head) > > offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32); > msg = (u32 *)(msi->eq_cpu + offs); > - hwirq = *msg & IPROC_MSI_EQ_MASK; > + hwirq = readl(msg); > + hwirq = (hwirq >> 5) + (hwirq & 0x1f); > > /* > * Since we have multiple hwirq mapped to a single MSI vector,nnn > Change looks okay to me in general. May I know which platform you tested this patch on and was SMP affinity configuration tested? Thanks, Ray