From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752691AbdJLMjn (ORCPT ); Thu, 12 Oct 2017 08:39:43 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:46234 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751502AbdJLMjm (ORCPT ); Thu, 12 Oct 2017 08:39:42 -0400 Subject: Re: [PATCH] iommu: enable bypass transaction caching for ARM SMMU 500 To: Feng Kan , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, will.deacon@arm.com, rrichter@redhat.com, herton@redhat.com References: <1507759719-16675-1-git-send-email-fkan@apm.com> From: Robin Murphy Message-ID: Date: Thu, 12 Oct 2017 13:39:39 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <1507759719-16675-1-git-send-email-fkan@apm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/10/17 23:08, Feng Kan wrote: > The ARM SMMU identity mapping performance was poor compared with the > DMA mode. It was found that enable caching would restore the performance > back to normal. The S2CRB_TLBEN bit in the ACR register would allow for > caching of the stream to context register bypass transaction information. I know the hardware design and reasoning behind this feature, but I'm still a little surprised that bypass can show a measurably higher overhead than the full DMA mapping path in practice. MMU-500 is great :D > Signed-off-by: Feng Kan > --- > drivers/iommu/arm-smmu.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index 3bdb799..b5676a8 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -59,6 +59,7 @@ > #define ARM_MMU500_ACTLR_CPRE (1 << 1) > > #define ARM_MMU500_ACR_CACHE_LOCK (1 << 26) > +#define ARM_MMU500_ACR_S2CRB_TLBEN (1 << 10) > #define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8) > > #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ > @@ -1606,7 +1607,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) > * Allow unmatched Stream IDs to allocate bypass > * TLB entries for reduced latency. > */ > - reg |= ARM_MMU500_ACR_SMTNMB_TLBEN; > + reg |= ARM_MMU500_ACR_SMTNMB_TLBEN | ARM_MMU500_ACR_S2CRB_TLBEN; > writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR); > } > Looks correct to me, and TLB usage by bypass domains should still be equivalent to that of translation domains, so I don't think we should see any deleterious effects overall: Reviewed-by: Robin Murphy