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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-26980053078sm125956445ad.10.2025.09.22.01.26.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Sep 2025 01:26:50 -0700 (PDT) Message-ID: Date: Mon, 22 Sep 2025 16:26:43 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 06/14] phy: qcom: qmp-usbc: Add USB/DP switchable PHY clk register To: Dmitry Baryshkov Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio References: <20250919-add-displayport-support-for-qcs615-platform-v5-0-eae6681f4002@oss.qualcomm.com> <20250919-add-displayport-support-for-qcs615-platform-v5-6-eae6681f4002@oss.qualcomm.com> From: Xiangxu Yin In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: CHI-OZgpzn5OIXLy5wRGifOfSN-_Yi-Y X-Authority-Analysis: v=2.4 cv=YMOfyQGx c=1 sm=1 tr=0 ts=68d1084c cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=0ewKxBccC1tKemf2ImcA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAwNCBTYWx0ZWRfX+9sFtovwSeto 8MNrOP8dfjocBMaDpMd/hBP8Jiy0rB7J5mEb+iNKro2vnb9BxfoC/RkB5IJZ8qAe4vvhmOcX1ED mx+esIsYP4RWWCqZUmjv9Eu6rG3RXRDlHv8Raw5gXx2Wy8VP7x9G5dxASywXIigjxiQykgkeHFc ZHo/1iUiG1WGgvj9h107N90/HnJvF/MPwqK/MlJ2ZugI1J6YdxroiiITSPA0QNLDVU0UXddAItf WKxhUcfmr8WD3TSewZXQOylnJa8fLynKrDccPBJCn0HbqsAClyJLAIjqTUEDq2rTE8nettTefqT LvQzjLT+5beIm1xsBwnUMzaFUU1tdwTe+65UzmIYbSpldUKjla1Gk1nGE2SA2OnY/VeoXRWo7Xb 0MQzMToS X-Proofpoint-ORIG-GUID: CHI-OZgpzn5OIXLy5wRGifOfSN-_Yi-Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-22_01,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 adultscore=0 priorityscore=1501 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200004 On 9/20/2025 12:46 AM, Dmitry Baryshkov wrote: > On Fri, Sep 19, 2025 at 10:24:23PM +0800, Xiangxu Yin wrote: >> Add USB/DP switchable PHY clock registration and DT parsing for DP offsets. >> Extend qmp_usbc_register_clocks and clock provider logic to support both >> USB and DP instances. > Why? Shall I update commit msg as below? "phy: qcom: qmp-usbc: add DP link and vco_div clocks for DP PHY USB3DP PHY requires link and vco_div clocks when operating in DP mode. Extend qmp_usbc_register_clocks and the clock provider logic to register these clocks along with the existing pipe clock, to support both USB and DP configurations." >> Signed-off-by: Xiangxu Yin >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 210 ++++++++++++++++++++++++++++++- >> 1 file changed, 204 insertions(+), 6 deletions(-) >>