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Wed, 15 Jul 2026 02:11:59 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: ASU80-mPZ9gg Date: Wed, 15 Jul 2026 08:11:39 +0200 From: "Arnd Bergmann" To: "David Laight" Cc: "Pedro Falcato" , "Yeoreum Yun" , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, Linux-Arch , kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, x86@kernel.org, linux-mm@kvack.org, kasan-dev@googlegroups.com, "linux-csky@vger.kernel.org" , linux-m68k@lists.linux-m68k.org, "linux-openrisc@vger.kernel.org" , "David Hildenbrand (Red Hat)" , "Russell King" , "Andrew Morton" , "Ankur Arora" , "Mike Rapoport" , "Magnus Lindholm" , "Christophe Leroy" , "Klara Modin" , "Huacai Chen" , "WANG Xuerui" , "Kirill A. Shutemov" , zhangtianyang@loongson.cn, wangyuli@aosc.io, "Thomas Bogendoerfer" , "Lorenzo Stoakes" , "Jason Gunthorpe" , "Catalin Marinas" , "Will Deacon" , "Ryan Roberts" , "Pasha Tatashin" , "Rohan McLure" , "Baolin Wang" , "Tejun Heo" , "Kevin Brodsky" , "Anup Patel" , atish.patra@linux.dev, "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , "Dave Hansen" , "Andy Lutomirski" , "Peter Zijlstra" , "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H. Peter Anvin" , "Johannes Weiner" , "Michal Hocko" , qi.zheng@linux.dev, "Shakeel Butt" , "Kairui Song" , "Barry Song" , "Axel Rasmussen" , "Yuanchu Xie" , "Wei Xu" , "Andrey Ryabinin" , "Alexander Potapenko" , "Andrey Konovalov" , "Dmitry Vyukov" , "Vincenzo Frascino" , "Anshuman Khandual" , "Yang Shi" , chaitanyas.prakash@arm.com, "Ard Biesheuvel" , guoren , yang.li85200@gmail.com, "Alexander Viro" , "Dinh Nguyen" , "schuster.simon@siemens-energy.com" , "Vivian Wang" , junhui.liu@pigmoral.tech, "Muchun Song" , "Vishal Moola (Oracle)" , "Nam Cao" , "Pavel Machek" , djbw@kernel.org, yu-cheng.yu@intel.com, "Baolu Lu" , "Jonathan Cameron" , "Coiby Xu" , "Andreas Larsson" , "Liam R. Howlett" , "Vlastimil Babka (SUSE)" , "Suren Baghdasaryan" , "Michal Hocko" , "Geert Uytterhoeven" , "Stafford Horne" , "Jonas Bonn" , "Stefan Kristiansson" Message-Id: In-Reply-To: <20260714224553.583c8445@pumpkin> References: <20260713135614.1618183-1-yeoreum.yun@arm.com> <20260713135614.1618183-3-yeoreum.yun@arm.com> <20260714143450.61a94085@pumpkin> <20260714224553.583c8445@pumpkin> Subject: Re: [RFC PATCH 02/34] ARM: mm: make 2-level pgd_t a scalar Content-Type: text/plain Content-Transfer-Encoding: 7bit On Tue, Jul 14, 2026, at 23:45, David Laight wrote: > On Tue, 14 Jul 2026 17:06:00 +0200 > "Arnd Bergmann" wrote: > > For the 2-level page table, this only concerns pgd_t, which is > > rarely passed around or returned by value. The 3-level page > > table has a 64-bit pte_t, which means we probably won't > > want STRICT_MM_TYPECHECKS there. > > Is the 64bit pte_t needed to get the extra modified and accessed > flags there aren't free bits for in the hardware pte? > Would it have been possible to use bits that are fixed in the hardware > pte for the extra bits and write the value to pte[0] and pte[256] fixing > up the value written to pte[0] (that the hardware reads). The 64-bit pte_t for 3-level tables (armv7ve/lpae) is the hardware table entry, following the same format as arm64, and similar to how x86/pae works. The special cases with double pmd_t entries four 1024 byte tables to hold hardware and software entries that David Hildenbrand cited is only for the old 2-level tables (armv3 through armv7-a). The Linux pte_t is only 32-bit wide here, and gets copied into the CPU specific hardware pte in the cpu_*_set_pte_ext() function. Arnd