From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=68.232.154.123 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794398195; b=U0FLz3RyPvXsEEUj7JQSbKpgjIqEoCCf2JECEnK9zxea8C0mVQZtjsKdaBgI7AgstOR5 ezpQSMJqth9f/gvKtOl0/Ox2cGiEQNorHKw65prbwiu5KrncoNunaQ0CnfhuNYIjSAgZK JCCI7CmTsriDVSLJKQA2ZkbsZNg7rHFAFRZfWW85RIy/uiRqXl/p/E2Ny6VMljy13xHMP SGAd2uvREnRYrvZzy4O1yQlXFsr70EUPaIl5nCq2p5GryR7gxl2SBNu3qRSaxIk8qlJPj 5rvF/gMhBz1SJ3qRZCIMl2du9A0/gQc7AxPG89t2r+6AIUm1Xze9hiJOAJ9z8SUEL0g== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794398195; h=DMARC-Filter:DKIM-Signature:X-CSE-ConnectionGUID:X-CSE-MsgGUID: X-IronPort-AV:X-Amp-Result:Received:Received:Received:From:To:CC: Subject:Date:Message-ID:X-Mailer:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding:Content-Type; bh=DWUyvR0mcuN0V5jDM7w8yZYLxYHJp4UJ9kKOjvMXF1c=; b=XQAJ+S0/WqNcbmVowVfiYqC8YAX8xXxTH+pRKCfWnFpjYKJXvtHjd8HBGM9VE4g1uk2N qcQYIB36M5Kds4MtH+hRZ2ag6RtLxm0K0GroR5bwoOc+sRr/b53mMC3Qfm2cOvWWNECWr YwKIEozdlPmmTvqb/iZ/URVQWFmG7ctWOnyXpXWJanFLrNILfbVB8logZnclRry1Xu9hC SME10ZsATemzCuocyjRx/8KVzRm+HOzWAGhbcpaGyvlh06IbN8a0paRm86BSfWAiirsjd UTJoSioYmyinpkn5mSsIsoNfrMK2wxyeaS/trEbB0iD8d+icKcby4akrPXxypqZOpvQ== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=dYhBjvqA; arc=none smtp.remote-ip=68.232.154.123 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 144D6606A326; Wed, 11 Nov 2026 11:56:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 144D6606A326 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=dYhBjvqA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1794398195; x=1825934195; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ieerc5KGxRLTD1EfIK8aZee4oj4EX2JFlQ5c/nOv8BU=; b=dYhBjvqAHEZzJqElgcbM8j92SL7T7vxr0zZp9D2FUGsuYET/o3kCOV9M mz/vgeLEp1SSpE+s2lbnn2MHr5zfw4tgrduc9sKNaCpu5xJJUM2nKrHbx u39YRmE/vrfMVTb7/syuP6OzcX7lj5uhkMYy/Z/r6XgGXmux3rBk4vIPc GHq6Fa1YS/3HG0JkFKGt/A2rIybbEf89VzjRbNaJiPAWvh6+bNbx2EG9k 5FYctgvLxV8GXU2B79EDHPCOIpdBMkGgUzU5sBghYE8HRyIIbUZS9OFeY PzPstqUtq6//tIWQT0bjbW5wLJPlsxVEe27pkkedDabC9tIythtsa2oaD g==; X-CSE-ConnectionGUID: m/1eTM7sT/2juqgGuAxWtw== X-CSE-MsgGUID: HxSL80FNRzah36yOaHYLGg== X-IronPort-AV: E=Sophos;i="6.27,207,1787036400"; d="scan'208";a="66592262" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Nov 2026 04:56:34 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.56; Wed, 11 Nov 2026 04:56:33 -0700 Received: from che-ll-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 11 Nov 2026 04:56:24 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v10 4/8] mtd: spi-nor: sfdp: expose the SFDP as a read-only NVMEM device Date: Wed, 11 Nov 2026 17:25:36 +0530 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain The SPI NOR core already reads the SFDP tables during enumeration and caches them in nor->sfdp->dwords (see spi_nor_parse_sfdp()). Re-expose that cached data as a read-only NVMEM device, in on-flash byte order, rooted at the flash's SFDP child node (compatible "jedec,sfdp"). This lets NVMEM cells reference any SFDP data: a fixed-layout for parameters at a known offset, or an nvmem-layout parser for vendor data whose location must be discovered at runtime. Reviewed-by: Miquel Raynal Reviewed-by: Michael Walle Signed-off-by: Manikandan Muralidharan --- drivers/mtd/spi-nor/core.c | 75 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 90524c58602e..a034dce7c839 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -2816,6 +2817,72 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor) } } +static int spi_nor_sfdp_reg_read(void *priv, unsigned int offset, + void *val, size_t bytes) +{ + struct spi_nor *nor = priv; + struct sfdp *sfdp = nor->sfdp; + size_t sfdp_size = sfdp->num_dwords * sizeof(*sfdp->dwords); + + if (offset >= sfdp_size || bytes > sfdp_size - offset) + return -EINVAL; + + /* The cached SFDP is kept in on-flash (little-endian) byte order. */ + memcpy(val, (u8 *)sfdp->dwords + offset, bytes); + + return 0; +} + +/** + * spi_nor_register_sfdp_nvmem() - expose the SFDP as a read-only NVMEM device + * @nor: pointer to a 'struct spi_nor' + * + * Expose the whole SFDP, in on-flash byte order, as a read-only NVMEM device + * rooted at the flash's SFDP child node (compatible "jedec,sfdp"), if any. + * This lets generic (fixed-layout) or vendor (nvmem-layout) cells reference + * any SFDP data. + * + * Return: 0 on success or if there is nothing to do, -errno otherwise. + */ +static int spi_nor_register_sfdp_nvmem(struct spi_nor *nor) +{ + struct device *dev = nor->dev; + struct nvmem_config config = { }; + struct nvmem_device *nvmem; + struct device_node *np; + + if (!nor->sfdp) + return 0; + + np = of_get_compatible_child(dev_of_node(dev), "jedec,sfdp"); + + config.dev = dev; + config.of_node = np; + config.name = "sfdp"; + config.id = NVMEM_DEVID_AUTO; + config.owner = THIS_MODULE; + config.read_only = true; + config.word_size = 1; + config.stride = 1; + config.size = (int)(nor->sfdp->num_dwords * sizeof(*nor->sfdp->dwords)); + config.reg_read = spi_nor_sfdp_reg_read; + config.priv = nor; + + nvmem = devm_nvmem_register(dev, &config); + of_node_put(np); + if (IS_ERR(nvmem)) { + /* NVMEM support is optional. */ + if (PTR_ERR(nvmem) == -EOPNOTSUPP) + return 0; + return dev_err_probe(dev, PTR_ERR(nvmem), + "failed to register SFDP NVMEM device\n"); + } + + dev_dbg(dev, "exposed %d-byte SFDP as an NVMEM device\n", config.size); + + return 0; +} + /** * spi_nor_late_init_params() - Late initialization of default flash parameters. * @nor: pointer to a 'struct spi_nor' @@ -2980,6 +3047,14 @@ static int spi_nor_init_params(struct spi_nor *nor) return ret; } + /* + * Expose the SFDP table as an NVMEM device only when + * the flash actually provides one + */ + ret = spi_nor_register_sfdp_nvmem(nor); + if (ret) + return ret; + ret = spi_nor_late_init_params(nor); if (ret) return ret; -- 2.43.0