Re: [PATCH RESEND 1/3] drm/panel: sitronix-st7789v: fix timing for jt240mhqs_hwt_ek_e3 panel

[Jessica Zhang <quic_jesszhan@quicinc.com>]

On 5/28/2024 1:32 AM, Gerald Loacker wrote:
> Flickering was observed when using partial mode. Moving the vsync to the
> same position as used by the default sitronix-st7789v timing resolves this
> issue.
> 
> Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net>

Hi Gerald,

Just wondering, are these new timing values taken from the panel specs? 
If the timing in the original patch was wrong, maybe we need a fixes tag.

Acked-by: Jessica Zhang <quic_jesszhan@quicinc.com>

Thanks,

Jessica Zhang

> ---
>   drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7789v.c b/drivers/gpu/drm/panel/panel-sitronix-st7789v.c
> index 88e80fe98112..32e5c0348038 100644
> --- a/drivers/gpu/drm/panel/panel-sitronix-st7789v.c
> +++ b/drivers/gpu/drm/panel/panel-sitronix-st7789v.c
> @@ -286,9 +286,9 @@ static const struct drm_display_mode jt240mhqs_hwt_ek_e3_mode = {
>   	.hsync_end = 240 + 28 + 10,
>   	.htotal = 240 + 28 + 10 + 10,
>   	.vdisplay = 280,
> -	.vsync_start = 280 + 8,
> -	.vsync_end = 280 + 8 + 4,
> -	.vtotal = 280 + 8 + 4 + 4,
> +	.vsync_start = 280 + 48,
> +	.vsync_end = 280 + 48 + 4,
> +	.vtotal = 280 + 48 + 4 + 4,
>   	.width_mm = 43,
>   	.height_mm = 37,
>   	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
> 
> -- 
> 2.37.2
>