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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b009ae4f2ddsm1374396066b.82.2025.09.04.05.27.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Sep 2025 05:27:07 -0700 (PDT) Message-ID: Date: Thu, 4 Sep 2025 14:27:04 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V5 4/4] arm64: dts: qcom: sm8550: Add max-sd-hs-hz property To: Krzysztof Kozlowski , Sarthak Garg , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com References: <20250903080404.3260135-1-quic_sartgarg@quicinc.com> <20250903080404.3260135-5-quic_sartgarg@quicinc.com> <6deac56f-e21a-4447-bfa7-a414084676b8@kernel.org> <23c29fb7-c0a4-4519-9b8d-e68255b83a10@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: JuA5JdXm1wAxm75qqU09kaYUC5ERCdKS X-Proofpoint-ORIG-GUID: JuA5JdXm1wAxm75qqU09kaYUC5ERCdKS X-Authority-Analysis: v=2.4 cv=ccnSrmDM c=1 sm=1 tr=0 ts=68b9859e cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=noZB7YPBI9-alL1Zr8wA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDA0MiBTYWx0ZWRfX4EEQqkFJmtYK aLKwwkmkLccbUAaHENPjt5PVmaI47ZHDUniRbjG1Qu1uSfkksJyNmVHSrtg3ubA23tr3l2ZLMab tM6cCpiTYHhKEPy+zeFCsCpHmsdwKsCsMhJeRKA4pHRbMRZUo6ZIkenOt3SHJF+eOWuazVRv4wt Gi4gJ08nJe+oaXF0tPDhsaoJ5DyHmluIG+nwuWRQehTRDUST6HN95MOqiD8iObaGf46Dg31oiqE NljKAoj8gIr3FDm0Nk3q7PplTB5xL8cdWXxCDqAFK0vqPfdW/T6TroiuZ+IR+v4AocHDIl9L+NA iKle1wSS+AOO7s8yzHRd5HrvpEFCrMzFLVFob4cngn6XxNAZeC7Tf4MobobxZnQLvquky+EHpuc jGbnqOpA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-04_04,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 suspectscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300042 On 9/4/25 12:52 PM, Krzysztof Kozlowski wrote: > On 04/09/2025 12:51, Krzysztof Kozlowski wrote: >> On 04/09/2025 10:36, Konrad Dybcio wrote: >>> On 9/3/25 10:21 AM, 'Krzysztof Kozlowski' via kernel wrote: >>>> On 03/09/2025 10:04, Sarthak Garg wrote: >>>>> Due to board-specific hardware constraints particularly related >>>>> to level shifter in this case the maximum frequency for SD High-Speed >>>>> (HS) mode must be limited to 37.5 MHz to ensure reliable operation of SD >>>>> card in HS mode. >>>>> >>>>> This is achieved by introducing the `max-sd-hs-hz` property in the >>>>> device tree, allowing the controller to operate within safe frequency >>>>> limits for HS mode. >>>>> >>>> >>>> Probably we will now replicate the same discussion... And it will be >>>> happening every time you send the same and not reflect it in commit msg. > > Just to emphasize this - it will happen EVERY time. > >>>> >>>> Bindings say board setup, this commit msg says board config, but the >>>> patch says SoC. This is not correct. >>> >>> Both are correct, looking at the problem from two perspectives. >>> >>> The bindings description mentions board-specific limitations (e.g. because >>> "the board's electrical design does not allow one to achieve the full rated >>> frequency that the SoC can otherwise do, in a stable way") >>> >>> Here the author tries to argue that almost all SM8550 boards are broken >>> in this sense, because the reference design did not feature the required >>> passive components, making most (derivative) designs sort of "broken by >>> default" - and only some (if any?) vendors decided to go with the >>> additional components required to lift this limitation. >>> >>> This in turn makes it fair to assume the developer experience would benefit >>> from having the SD card high speed modes always work (with the slight speed >>> cap which may not be required for the 1 or 2 designs that took the extra >>> step) without each board DT creator having to track down this property >>> separately. >> >> And then if you send same v3, I will ask the same. Can the author > > v3 -> v6 So, would you be accepting of this patch if the commit message was: arm64: dts: qcom: sm8550: Limit max SD HS mode frequency by default Due to an implementation detail in this SoC, additional passive electrical components are required to achieve the maximum rated speed of the SD controller when paired with a High-Speed SD Card. Without them, the clock frequency must be limited to 37.5 MHz for link stability. Because the reference design does not contain these components, most (derivative) boards do not have them either. To accommodate for that, apply the frequency limit by default and delegate lifting it to the odd boards that do contain the necessary onboard hardware. Konrad