From: Andrew Cooper <andrew.cooper3@citrix.com>
To: bp@kernel.org
Cc: bp@alien8.de, linux-kernel@vger.kernel.org, x86@kernel.org
Subject: Re: [PATCH] x86/microcode/AMD: Limit Entrysign signature checking to known generations
Date: Mon, 27 Oct 2025 14:47:24 +0000 [thread overview]
Message-ID: <d12bbb56-8ce4-477c-a7a6-600909374734@citrix.com> (raw)
In-Reply-To: <20251023124629.5385-1-bp@kernel.org>
> Limit Entrysign sha256 signature checking to CPUs in the range Zen1-Zen5.
>
> ...
> +static bool cpu_has_entrysign(void) +{ + unsigned int fam =
> x86_family(bsp_cpuid_1_eax); + unsigned int model =
> x86_model(bsp_cpuid_1_eax); + + if (fam == 0x17) + return true; + + if
> (fam == 0x19) { + if (model <= 0x2f || + (0x40 <= model && model <=
> 0x4f) || + (0x60 <= model && model <= 0x6f)) + return true; + } + +
> return false; +}
That's Zen1-3. It's Fam 0x1a you need to split to separate Zen5 and 6.
~Andrew
next prev parent reply other threads:[~2025-10-27 14:47 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-23 12:46 Borislav Petkov
2025-10-27 14:47 ` Andrew Cooper [this message]
2025-10-27 16:02 ` Borislav Petkov
2025-10-27 16:31 ` [tip: x86/urgent] " tip-bot2 for Borislav Petkov (AMD)
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