From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2FE027F75F for ; Wed, 23 Jul 2025 08:07:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753258023; cv=none; b=A3shJDcGq8sUfKEF3xSoWJVQxo5wypgiXPA8hJ4Syv4PI00eOc9D7lVZfAF3qTDxeuPdJ33qqM9BHpDKUbQbQE7kn6+BtGHHn+nR4Jv4OedXlWn/sRHUYKiBXQ9aJEJI1YiGsQIN0kv4vWPazA+fTAvBauPljEcDaWUW8+ZL9D4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753258023; c=relaxed/simple; bh=8aecLTAzLm8TXTXNAqv86bF9B9YQxFXwXcdqeERA7Z8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=afVja7lExLUuliatICLe8ZXzWTXStbqDJsszmBrs/cWLJtmjLho7IVIh1qUFkNgC6DOO3dxYxeI2t9rZuHf7A9gnB3wB0wbwDwQHKFVHWl8HkCSNOvibbQI7x/3WdSfNUebjPmg4wwS+E0J11eN++JwFlCGr+dNKpVRgVb41trQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=IQUIsMIt; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="IQUIsMIt" Received: from [192.168.88.20] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id C8819C66; Wed, 23 Jul 2025 10:06:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1753257980; bh=8aecLTAzLm8TXTXNAqv86bF9B9YQxFXwXcdqeERA7Z8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=IQUIsMItpWJDPqoFjfn9sUxnY1GzstPIpRxIB/NkzRo20ERg3SMuBDJt9f0YYWkLD 6HQw7ZNE4kFZfglV9tpgu0R1ogEgZm5zqjEd3rBJFL4FEun+KOKypWHJIbBGNUyHOz lxXVmolGm76zDlpzHk7ynhhTE3OUQQGR0tFjrLug= Message-ID: Date: Wed, 23 Jul 2025 11:06:54 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/2] phy: cadence: cdns-dphy: Update calibration wait time for startup state machine To: Devarsh Thakkar Cc: aradhya.bhatia@linux.dev, s-jain1@ti.com, r-donadkar@ti.com, j-choudhary@ti.com, a0512644@ti.com, vkoul@kernel.org, kishon@kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250704125915.1224738-1-devarsht@ti.com> <20250704125915.1224738-3-devarsht@ti.com> Content-Language: en-US From: Tomi Valkeinen Autocrypt: addr=tomi.valkeinen@ideasonboard.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, On 04/07/2025 15:59, Devarsh Thakkar wrote: > Do read-modify-write so that we re-use the characterized reset value as > specified in TRM [1] to program calibration wait time which defines number > of cycles to wait for after startup state machine is in bandgap enable > state. > > This fixes PLL lock timeout error faced while using RPi DSI Panel on TI's > AM62L and J721E SoC since earlier calibration wait time was getting > overwritten to zero value thus failing the PLL to lockup and causing > timeout. > > [1] AM62P TRM (Section 14.8.6.3.2.1.1 DPHY_TX_DPHYTX_CMN0_CMN_DIG_TBIT2): > Link: https://www.ti.com/lit/pdf/spruj83 > > Cc: stable@vger.kernel.org > Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support") > Signed-off-by: Devarsh Thakkar > --- > V4: No change > V3: > - Do read-modify-write to preserve reset value for calibration wait > time > V2: > Introduced this as as separate patch > > drivers/phy/cadence/cdns-dphy.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c > index da8de0a9d086..24a25606996c 100644 > --- a/drivers/phy/cadence/cdns-dphy.c > +++ b/drivers/phy/cadence/cdns-dphy.c > @@ -30,6 +30,7 @@ > > #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) > #define DPHY_CMN_SSM_EN BIT(0) > +#define DPHY_CMN_SSM_CAL_WAIT_TIME GENMASK(8, 1) > #define DPHY_CMN_TX_MODE_EN BIT(9) > > #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40) > @@ -410,7 +411,8 @@ static int cdns_dphy_power_on(struct phy *phy) > writel(reg, dphy->regs + DPHY_BAND_CFG); > > /* Start TX state machine. */ > - writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN, > + reg = readl(dphy->regs + DPHY_CMN_SSM); > + writel((reg & DPHY_CMN_SSM_CAL_WAIT_TIME) | DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN, > dphy->regs + DPHY_CMN_SSM); That's not how you do read-modify-write. You should first read the register, then clear the fields you want to set/clear, then set the fields, then write. reg = readl(dphy->regs + DPHY_CMN_SSM, dphy->regs + DPHY_CMN_SSM); reg &= ~(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN) reg |= DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN; writel(reg, dphy->regs + DPHY_CMN_SSM); That's the general form, in this particular case the and-line is not necessary, of course. There's also FIELD_MODIFY() (and related), but I'm not sure if I like them... Up to you. Tomi