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Thu, 9 Apr 2026 08:46:35 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: ADDaTlyNV6JN Date: Thu, 09 Apr 2026 14:46:15 +0200 From: "Ard Biesheuvel" To: "Eric Biggers" , "Simon Richter" Cc: "John Paul Adrian Glaubitz" , linux-crypto@vger.kernel.org, "Herbert Xu" , linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, x86@kernel.org, "Harald Freudenberger" , "Holger Dengler" Message-Id: In-Reply-To: <20260327172423.GA3407398@google.com> References: <20260326201246.57544-1-ebiggers@kernel.org> <0982d4341f58e2f1181bc472dc9c9d8542148e3c.camel@physik.fu-berlin.de> <20260326202733.GA2657@quark> <35e00d0f-85f6-457a-99b4-703caf3e1e6e@hogyros.de> <20260327172423.GA3407398@google.com> Subject: Re: [PATCH 0/3] crypto: Remove arch-optimized des and des3_ede code Content-Type: text/plain Content-Transfer-Encoding: 7bit On Fri, 27 Mar 2026, at 18:24, Eric Biggers wrote: > On Fri, Mar 27, 2026 at 06:59:21PM +0900, Simon Richter wrote: ... >> However, even from the "crypto" perspective I believe that we can't get >> around support for asynchronous offload devices, because of mobile devices. >> I suspect no one would be building dedicated silicon for asynchronous AES >> into mobile CPUs if that wasn't worth it somehow > > They do it anyway. It's a checkbox feature. I.e. the purpose is for it > to be advertised on a list of features. > Often, h/w crypto IP blocks are part of the SoC-specific authenticated/confidential boot chain, which is anchored in the mask ROM. Nobody wants to put software implementations of RSA and AES in there, and so it offloads the crypto processing to a h/w block instead. Since the h/w block is there, it can be used by the OS too, but that doesn't mean doing so makes any sense. Only h/w accelerators with multiple internal queues can generally keep up with the CPUs and network/block I/O in a meaningful manner, and those are quite rare IME.