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X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iLSQNp/AUtrkHgq033xZ19OVebu4eIxYQ9Rk7RQ1KWlUyflN/BCW8RnkqrlAJjnJo6aQtcTjmeboTVWtHtXVK8SnulunNBnu2kjEg5X2RFs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR10MB6729 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-17_02,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 malwarescore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2510240000 definitions=main-2511170065 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE1MDAzMSBTYWx0ZWRfX3ndS+mU2Q0R5 7CzN/N8SoDgpTE0porPkOf5chfIqrsXTnhWckUX6/+QFMP/thh9lVpAki+q0luomnc2F1DniEgv zE1JrCeeDvQB+AU27PE+8dYgl6bRowTZ9UAp4L2ViGQHTl//JbODQktnFp30enTk8b6O1UHmG2r r6GgiQZ2VasEW+JkMCCz6Au2Qo9ljIAigxrf3ehuPg6I8k+WHASUJqNLLh+E2oU9N/GoxMOVSEQ 2oSSyg8xAF1unhF8iMeKU7f7AneUyu9GnQ6OtPitGUi40CiMGsI1z+WtZ9axEJ5MpG9EZFKXT+a UavF5PRIYvpoMhGI4VwDXVzjgh214nb5i3pxh8uSPT0kS+SuRfXOZ6z8jv168aJNuO9L+uOgFWF pRvG6EDpHWUqBy55dUF0a+hqFD6aGQ== X-Proofpoint-ORIG-GUID: 5EV86t3uE120YHxTtUnokDPNsK90mrKA X-Proofpoint-GUID: 5EV86t3uE120YHxTtUnokDPNsK90mrKA X-Authority-Analysis: v=2.4 cv=a+o9NESF c=1 sm=1 tr=0 ts=691ad3de b=1 cx=c_pps a=WeWmnZmh0fydH62SvGsd2A==:117 a=WeWmnZmh0fydH62SvGsd2A==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=z/mQ4Ysz8XfWz/Q5cLBRGdckG28=:19 a=lCpzRmAYbLLaTzLvsPZ7Mbvzbb8=:19 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=GoEa3M9JfhUA:10 a=VkNPw1HP01LnGYTKEx00:22 a=UOU8BSC-JFg9kLDGmaIA:9 a=QEXdDO2ut3YA:10 On 11/14/25 22:34, Josh Poimboeuf wrote: > On Fri, Nov 14, 2025 at 10:56:48AM +0100, Alexandre Chartre wrote: >>> Other than '!', the meaning of the flags isn't intuitive. Maybe it >>> should just show the source code names: >>> >>> ALT_NOT(X86_FEATURE_FOO) >>> >>> ALT_DIRECT_CALL(X86_FEATURE_BAR) >>> >>> ALT_UNKNOWN_FLAG(X86_FEATURE_BAZ) >>> >> >> I think '?' is meaningful too, but I wasn't sure about '+'. >> >> I am using single characters to keep the alternative name short. It can already >> be fairly long because of the feature name (like "X86_FEATURE_SPEC_STORE_BYPASS_DISABLE") >> >> Also I am assuming that flags can be combined (although that's not currently >> the case) so that would be more difficult with full ALT_* names and the >> result would be much longer. > > Ok. > >>>> - If an alternative is a jump table then "JUMP" is used as the feature >>>> name. >>> >>> Hm, it's a bit confusing to label a jump label as an "alternative" as >>> those are two distinct things (though I'm aware that objtool conflates >>> the two). >>> >>>> - If an alternative is an exception table then "EXCEPTION" is used as the >>>> feature name. >>> >>> Ditto. >>> >> >> Yes, the wording is not good, I use it just because objtool handles jump >> labels and exception tables as alternative. I will reword to something >> better. > > I meant not only the wording here, but also the "" > labels shown in the disassembly. > Right, I will change it , , . >>>> Disassembly can show default alternative jumping to .altinstr_aux >>>> ----------------------------------------------------------------- >>>> Disassembly can show a default alternative jumping to .altinstr_aux. This >>>> happens when the _static_cpu_has() function is used. Its default code >>>> jumps to .altinstr_aux where a test sequence is executed (test; jnz; jmp). >>>> >>>> At runtime, this sequence is not used because the _static_cpu_has() >>>> an alternative with the X86_FEATURE_ALWAYS feature. >>>> >>>> >>>> debc: perf_get_x86_pmu_capability+0xc jmpq 0xdec1 <.altinstr_aux+0xfc> | NOP5 (X86_FEATURE_HYBRID_CPU) | jmpq 0x61a (X86_FEATURE_ALWAYS) # >>> >>> I'm finding this one-line format considerably more difficult to parse >>> than the slightly longer two-line form: >>> >>> debc: perf_get_x86_pmu_capability+0xc | X86_FEATURE_HYBRID_CPU | X86_FEATURE_ALWAYS >>> debc: perf_get_x86_pmu_capability+0xc jmpq 0xdec1 <.altinstr_aux+0xfc> | NOP5 | jmpq 0x61a >> >> >> Another option could be: >> >> debc: perf_get_x86_pmu_capability+0xc jmpq 0xdec1 <.altinstr_aux+0xfc> () | >> NOP5 (X86_FEATURE_HYBRID_CPU) | >> jmpq 0x61a (X86_FEATURE_ALWAYS) >> >> I think I will use this option when displaying alternative one after the other, >> and your suggestion when displaying side-by-side, and add an option to select >> the display. > > Hm, but how would that "one after the other" display look for an > alternative with multiple instructions? A "compact vs wide" option is > ok, but within each of those I think it's helpful to use a consistent > format regardless of whether the alternative has one or multiple > instructions. > David raises the issue that a side-by-side display requires a large window. The compact display could be like this: Alternative with single instruction: bb8: do_one_initcall+0x1a8 = callq *0x0(%rip) # 0xbbe (if default) = sti (if !X86_FEATURE_XENPV) = callq BUG_func (if +X86_FEATURE_ALWAYS) Alternative with multiple instructions: 82e7: __switch_to_asm+0x27 = DEFAULT 82e7: __switch_to_asm+0x27 | jmp 0x8312 <__switch_to_asm+0x52> | = !X86_FEATURE_ALWAYS 82e7: __switch_to_asm+0x27 | NOP1 82e8: __switch_to_asm+0x28 | NOP1 82e9: __switch_to_asm+0x29 | callq 0x82ef <__switch_to_asm+0x2f> 82ee: __switch_to_asm+0x2e | int3 82ef: __switch_to_asm+0x2f | add $0x8,%rsp 82f3: __switch_to_asm+0x33 | lfence | = X86_FEATURE_RSB_CTXSW 82e7: __switch_to_asm+0x27 | mov $0x10,%r12 82ee: __switch_to_asm+0x2e | callq 0x82f4 <__switch_to_asm+0x34> 82f3: __switch_to_asm+0x33 | int3 82f4: __switch_to_asm+0x34 | callq 0x82fa <__switch_to_asm+0x3a> 82f9: __switch_to_asm+0x39 | int3 82fa: __switch_to_asm+0x3a | add $0x10,%rsp 82fe: __switch_to_asm+0x3e | dec %r12 8301: __switch_to_asm+0x41 | jne 0x82ee <__switch_to_asm+0x2e> 8303: __switch_to_asm+0x43 | lfence 8306: __switch_to_asm+0x46 | movq $0xffffffffffffffff,%gs:0x0(%rip) # 0x20b <__x86_call_depth> | >>> Also, I wonder if we can make NOP5 lowercase (nop5), since it really is >>> just an instruction, not something special like a feature. >> >> This indicates that this is a pseudo instruction, NOP5 is actually nopl 0x00(%eax,%eax,1). >> Even NOP1 can be a simple nop but also xchg %rax,%rax. > > But it still represents a single instruction... I view it as a readable > shorthand rather than a pseudo instruction. > Ok. I will change to nop. >>>> 82e7: __switch_to_asm+0x27 | | !X86_FEATURE_ALWAYS | X86_FEATURE_RSB_CTXSW >>> >>> Are the alternatives swapped? I believe this comes from the following >>> code, so the !X86_FEATURE_ALWAYS column should be last? >>> >>> .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS) >>> ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \ >>> __stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \ >>> __stringify(nop;nop;__FILL_ONE_RETURN), \ftr2 >>> >>> .Lskip_rsb_\@: >>> .endm >> >> I will check but I process/print alternative in the order provided by >> objtool (in struct alternative) > > It's quite possible objtool has them in reverse order. The order > shouldn't matter for objtool validate_branch(), but definitely matters > here. > That's probably the issue. I think objtool reads alternatives in the right order but it adds each of them at the beginning of the same list. So they end up in reverse order in the list. Thanks, alex.