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Mon, 26 Jan 2026 05:10:51 -0800 (PST) X-Received: by 2002:a17:90b:1f8a:b0:34f:454f:69a9 with SMTP id 98e67ed59e1d1-353c4175b83mr3472671a91.28.1769433051254; Mon, 26 Jan 2026 05:10:51 -0800 (PST) Received: from [192.168.29.125] ([49.43.234.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3536dc3e1aasm8680642a91.12.2026.01.26.05.10.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Jan 2026 05:10:50 -0800 (PST) Message-ID: Date: Mon, 26 Jan 2026 18:40:13 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] interconnect: qcom: glymur: Add Mahua SoC support To: Dmitry Baryshkov Cc: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Odelu Kukatla References: <20260123-mahua_icc-v1-0-bc82cb087f1e@oss.qualcomm.com> <20260123-mahua_icc-v1-2-bc82cb087f1e@oss.qualcomm.com> Content-Language: en-US From: Raviteja Laggyshetty In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI2MDExMiBTYWx0ZWRfX0xXWNmr4wT7k 8knvE6pQKumgehQI/hgUwlZIs1vJ8cyBakz8CAm8U6vfYH16cw2nhd6GOHFuxBUZTg7wCdhta0x FOpgfZSIeq2zRUjec0qy6K0nCatheE0Y3wQNpWkhrbhX5b268C0Dnas10JmpTgQ/3rnAQ9akcHX wXeEhvp81HcJQbF2XpiNTE1xSisWYWKBrN5jBsWQm3EInKLfCgyOS2XjBVnAVAZnYLRrEM95cpz 4dPAk5GuZimL6juvXeGdKREXchJH6BzJmpvkGSw8h84qLYJESVY6lsBTCsaZv4g9/VWCJt3lBkG BOJT0mmsuhBDFSAup2QSi9N72wNzDIWrqZt6OHQdMK48S/2Z+C49SWHZc5fqwtZJPD2C56ParWY NbMwJtXp4OPvyfMe6hgjIu3+i+TykJJaQOnwGa6LRMW3wKCbOs4vkrZngtatmA7ADoTC2FVtkPe K++Nx6TFOLzLoSCC0cA== X-Authority-Analysis: v=2.4 cv=RIq+3oi+ c=1 sm=1 tr=0 ts=697767dc cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=y/Pne2EoOvGgihOE/QD3VA==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=GM9RiBoW67VDSbq6NmgA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: q3xFyvKkzOkq5vPg4ytisV5_S3fQEOml X-Proofpoint-GUID: q3xFyvKkzOkq5vPg4ytisV5_S3fQEOml X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-26_03,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 phishscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601260112 On 1/23/2026 11:28 PM, Dmitry Baryshkov wrote: > On Fri, Jan 23, 2026 at 05:12:36PM +0000, Raviteja Laggyshetty wrote: >> Mahua is a derivative of the Glymur SoC. This patch extends the > > Documentation/process/submitting-patches.rst, look for 'This patch'. Will update the commit text, in next patch revision. > >> Glymur driver to support Mahua by: >> >> 1. Adding new node definitions for interconnects that differ from Glymur >> (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC). >> 2. Reusing existing Glymur definitions for identical NoCs. >> 3. Overriding the channel and buswidth, with Mahua specific values for >> the differing NoCs >> >> Co-developed-by: Odelu Kukatla >> Signed-off-by: Odelu Kukatla >> Signed-off-by: Raviteja Laggyshetty >> --- >> drivers/interconnect/qcom/glymur.c | 153 ++++++++++++++++++++++++++++++++++++- >> 1 file changed, 152 insertions(+), 1 deletion(-) >> >> +static struct qcom_icc_node * const mahua_cnoc_cfg_nodes[] = { > > As you are patching other instances, why can't we just patch out the > PCI_3A out of these structures? > >> >> +static int glymur_qnoc_probe(struct platform_device *pdev) >> +{ >> + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) { >> + llcc_mc.channels = 8; >> + ebi.channels = 8; >> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) { >> + qns_llcc.channels = 8; >> + chm_apps.channels = 4; >> + qnm_pcie_west.buswidth = 32; >> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) { >> + qns_pcie_west_mem_noc.buswidth = 32; >> + } > > Right here, set the node entries to NULL. cnoc_cfg_nodes is declared as an array of const pointers, so the pointer values cannot be reassigned after initialization. To change the addresses, the const qualifier would need to be dropped. To preserve const, the entire array has been duplicated instead by dropping the PCIE_3A related nodes. > >> + >> + return qcom_icc_rpmh_probe(pdev); >> +} >> + >> static const struct of_device_id qnoc_of_match[] = { >> { .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc}, >> { .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc}, >> @@ -2477,12 +2623,15 @@ static const struct of_device_id qnoc_of_match[] = { >> { .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc}, >> { .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt}, >> { .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg}, >> + { .compatible = "qcom,mahua-cnoc-cfg", .data = &mahua_cnoc_cfg}, >> { .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main}, >> { .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc}, >> + { .compatible = "qcom,mahua-hscnoc", .data = &mahua_hscnoc}, >> { .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc}, >> { .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc}, >> { .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc}, >> { .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt}, >> + { .compatible = "qcom,mahua-mc-virt", .data = &glymur_mc_virt}, >> { .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc}, >> { .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc}, >> { .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc}, >> @@ -2490,14 +2639,16 @@ static const struct of_device_id qnoc_of_match[] = { >> { .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc}, >> { .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc}, >> { .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc}, >> + { .compatible = "qcom,mahua-pcie-west-anoc", .data = &mahua_pcie_west_anoc}, >> { .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc}, >> + { .compatible = "qcom,mahua-pcie-west-slv-noc", .data = &mahua_pcie_west_slv_noc}, >> { .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc}, >> { } >> }; >> MODULE_DEVICE_TABLE(of, qnoc_of_match); >> >> static struct platform_driver qnoc_driver = { >> - .probe = qcom_icc_rpmh_probe, >> + .probe = glymur_qnoc_probe, >> .remove = qcom_icc_rpmh_remove, >> .driver = { >> .name = "qnoc-glymur", >> >> -- >> 2.43.0 >> >