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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-31429ff04absm37342978eec.8.2026.07.20.15.05.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Jul 2026 15:05:18 -0700 (PDT) Message-ID: Date: Mon, 20 Jul 2026 15:05:17 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] media: qcom: camss: Program CSIPHY common control registers To: Bryan O'Donoghue , Loic Poulain Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jigarkumar.zala@oss.qualcomm.com, gjorgji.rosikopulos@oss.qualcomm.com, hariramp@quicinc.com References: <20260717231331.1229693-1-anusha.nandi@oss.qualcomm.com> <20260717231331.1229693-2-anusha.nandi@oss.qualcomm.com> <530a9493-24c7-4812-8ada-591c7b63b651@oss.qualcomm.com> <286a1fc6-bd58-4ade-b183-e53776ba7a09@linaro.org> Content-Language: en-US From: Anusha Arun Nandi In-Reply-To: <286a1fc6-bd58-4ade-b183-e53776ba7a09@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIwMDIzOSBTYWx0ZWRfXxcaX/Dh3AqFd XUSd5iFsfxZqTikmr0HHCEgnEaoipqQrS8H6lOcB8qFv5JSNp9kUzu4kqP+Vm7Fen15yi1tyBP3 CihufDIeZgWa09sGZicnhi8C0aItT8I= X-Proofpoint-GUID: _rxmF2l699YXN_K_CC_kxBz7MwzwwWoU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIwMDIzOSBTYWx0ZWRfX+eEt0qQppuZi 47RtJx6W8klckVxT14TV5sFxKdgJv56y/sSbyscyQe47335/xyykNxmfZlMfn9g1+RpCfRSXAc6 WiOyfRW0VXRPVo0OJtkidjxlzkPCD71FHOw4hln1Tz63FLWlfhkQbwFLxBUxLJ2USd1oXh2q3en +t3f4AxiwG9i21d2lBzTkzk4LJqI2BBK7o8D83rsH8AdBtxpOnI7RyxfscOOHA0T2ouDnLozTnz mAzYd5bmvK07z3Rcco9ol4dkA+/7FNConhREqbOB4Rbton11cp08j8IDXE++sbwmq4A9rNICk5f hV5OY0H90DtLYQYIPnNAZ0ZZMwoi5Y9ENxuZrPJnH/EpldGeVyAVKT+t81kMfyOkSSeyfGUT0/d UEK4ZAONBLWfyewNJvqP2XTmZanT9daMIkf4proE3x9wriSW+xnhhV1ctALUdgsUkUOW9WIJ8Ob 3B4Ymudc6jvjc+JiJig== X-Authority-Analysis: v=2.4 cv=CpiPtH4D c=1 sm=1 tr=0 ts=6a5e9ba0 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=5T8G_QvBM0rgUmogAq8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: _rxmF2l699YXN_K_CC_kxBz7MwzwwWoU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_05,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607200239 On 7/20/2026 1:06 PM, Bryan O'Donoghue wrote: > On 20/07/2026 20:38, Anusha Arun Nandi wrote: >>> I don't really like this big camss-version switch case with magic, >>> which also introduces more magic values. Maybe we should have a >>> different version of csiphy_lanes_enable, based on the phy compatible >>> or revision. >>> >> Thank you for the feedback! We agree with your suggestion and will >> refactor this to use a version-specific implementation of >> csiphy_lanes_enable, based on the PHY compatible or revision, in the >> upcoming patchset. > > Hmm. > > Please don't do that. Instead work with David to get CPHY support into > the dedicated driver - including whatever additional work is required - > perhaps nothing more than reusing the existing dphy_opts structure for > cphy purposes. > > Proceeding in the direction elucidated above would mean inclusion of > four CPHYs into the exiting infrastructure - that's not "stopgap" that's > established precedent. > > A big no from me I'm afraid. > > There's a real upstream gap to be addresses for CPHY. Let's address it > not work-around it in a specific way for our platform. > > I'd expect to see some kind of subset of > > > include/linux/phy/phy-mipi-cphy.h > struct phy_configure_opts_mipi_cphy > > or perhaps we can reuse/abuse struct phy_configure_opts_mipi_dphy - for > example could it be changed into a generic structure to contain both > cphy and dphy data - with an appropriate name change ? > > My feeling is a phy_configure_opts_mipi_cphy structure is required but, > perhaps both cphy and dphy can exist in one structure or in a union of > structs. > > TBD > > deckard@sagittarius-a: /home/deckard/Development/qualcomm/qlt-kernel > git:(arm64-laptops-v7.2-rc1-camss-v6-ife-bringup) ✗ > ➜   grep dphy include/* -r > include/drm/bridge/dw_mipi_dsi.h:struct dw_mipi_dsi_dphy_timing { > include/drm/bridge/dw_mipi_dsi.h:             struct > dw_mipi_dsi_dphy_timing *timing); > include/linux/phy/phy.h:#include > include/linux/phy/phy.h: * @mipi_dphy:    Configuration set applicable > for phys supporting > include/linux/phy/phy.h:    struct phy_configure_opts_mipi_dphy    > mipi_dphy; > include/linux/phy/phy-mipi-dphy.h: * struct phy_configure_opts_mipi_dphy > - MIPI D-PHY configuration set > include/linux/phy/phy-mipi-dphy.h:struct phy_configure_opts_mipi_dphy { > include/linux/phy/phy-mipi-dphy.h:int > phy_mipi_dphy_get_default_config(unsigned long pixel_clock, > include/linux/phy/phy-mipi-dphy.h:                    struct > phy_configure_opts_mipi_dphy *cfg); > include/linux/phy/phy-mipi-dphy.h:int > phy_mipi_dphy_get_default_config_for_hsclk(unsigned long long hs_clk_rate, > include/linux/phy/phy-mipi-dphy.h:                          struct > phy_configure_opts_mipi_dphy *cfg); > include/linux/phy/phy-mipi-dphy.h:int > phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg); > include/linux/platform_data/media/mmp-camera.h:enum dphy3_algo { > include/linux/platform_data/media/mmp-camera.h:    int dphy[3];        / > * DPHY: CSI2_DPHY3, CSI2_DPHY5, CSI2_DPHY6 */ > include/linux/platform_data/media/mmp-camera.h:    enum dphy3_algo > dphy3_algo;    /* algos for calculate CSI2_DPHY3 */ > include/media/ipu-bridge.h:    u32 dphylinkenfuses; > deckard@sagittarius-a: /home/deckard/Development/qualcomm/qlt-kernel > git:(arm64-laptops-v7.2-rc1-camss-v6-ife-bringup) ✗ > ➜   grep cphy include/* -r > include/media/v4l2-mediabus.h: * enum > v4l2_mbus_csi2_cphy_line_orders_type - CSI-2 C-PHY line order > include/media/v4l2-mediabus.h:enum v4l2_mbus_csi2_cphy_line_orders_type { > include/media/v4l2-mediabus.h:    enum > v4l2_mbus_csi2_cphy_line_orders_type > line_orders[V4L2_MBUS_CSI2_MAX_DATA_LANES]; > > deckard@sagittarius-a: /home/deckard/Development/qualcomm/qlt-kernel > git:(arm64-laptops-v7.2-rc1-camss-v6-ife-bringup) ✗ > ➜ > > But to be 100% - I'm fully against burying inline CPHY code into CAMSS. > > The long term objective of cleaning things up and reducing technical > debt can't be realised by - adding more technical debt. > > And I'll reiterate the right-thing-to-do (tm) is to expand the kernel's > understanding/definition of PHYs to encompass CPHY for the benefit of > users and the entire community - instead of a qcom-specific hack. > > --- > bod We understand your concern here. We will work with David to integrate C-PHY support into the dedicated driver infrastructure, and explore the appropriate path for a phy_configure_opts_mipi_cphy structure — whether as a standalone header or as an extension of the existing phy_configure_opts_mipi_dphy structure. Thank you for the detailed feedback.