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([2a01:e0a:3d9:2080:dc4b:4af3:f382:7aa7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b47c29c9dsm37952745e9.4.2025.08.20.07.35.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Aug 2025 07:35:17 -0700 (PDT) Message-ID: Date: Wed, 20 Aug 2025 16:35:16 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC To: Anand Moon Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org References: <20240205171930.968-1-linux.amoon@gmail.com> <20240205171930.968-5-linux.amoon@gmail.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 20/08/2025 16:00, Anand Moon wrote: > Hi Neil, > > On Tue, 27 Feb 2024 at 18:34, Anand Moon wrote: >> >> Hi Niel, >> >> On Tue, 6 Feb 2024 at 20:31, wrote: >>> >>> On 06/02/2024 11:15, Anand Moon wrote: >>>> Hi Neil, >>>> >>>> On Tue, 6 Feb 2024 at 14:30, Neil Armstrong wrote: >>>>> >>>>> On 05/02/2024 18:19, Anand Moon wrote: >>>>>> As per S922X datasheet add missing cache information to the Amlogic >>>>>> S922X SoC. >>>>>> >>>>>> - Each Cortex-A53 core has 32 KB of instruction cache and >>>>>> 32 KB of L1 data cache available. >>>>>> - Each Cortex-A73 core has 64 KB of L1 instruction cache and >>>>>> 64 KB of L1 data cache available. >>>>>> - The little (A53) cluster has 512 KB of unified L2 cache available. >>>>>> - The big (A73) cluster has 1 MB of unified L2 cache available. >>>>> >>>>> Datasheet says: >>>>> The quad core Cortex™-A73 processor is paired with A53 processor in a big.Little configuration, with each >>>>> core has L1 instruction and data chaches, together with a single shared L2 unified cache with A53 >>>>> >>>> Ok, >>>> >>>> Since all the Cortex™-A73 and Cortex™-A53 share some improvements in >>>> the architecture with some improvements in cache features >>>> hence I update the changes accordingly. >>>> Also, I checked this in the ARM documentation earlier on this. >>> >>> I don't understand, Amlogic states it's a shared L2 cache, but you trust >>> the ARM documentation instead ??? >> >> Yes please find the Cortex™-A73 TRM >> L1 Cache >> https://developer.arm.com/documentation/100048/0002/level-1-memory-system/about-the-l1-memory-system?lang=en >> L2 Cache >> https://developer.arm.com/documentation/100048/0002/level-2-memory-system/about-the-l2-memory-system?lang=en >>> >>>> >>>>> And there's no indication of the L1 or L2 cache sizes. >>>> >>>> What I feel is in general all the Cortex™-A73 and Cortex™-A53 supports >>>> L1 and L2 cache size since it is part of the core features. >>>> but I opted for these size values from a Wikipedia article. >>>> >>>> On my Odroid N2+, I observe the following. >>>> >>>> I have also done some testing on the stress-ng to verify this. >>> >>> >>> Ok I don't feel confident adding numbers that comes out of thin air, >>> and even more since they are only shared to userspace. >>> >>> I think we should only add the numbers which are 100% sure >> >> Best way to let the Amlogic SoC members comment on the CPU L1/ / L2 cache size. >> But with the lack of pref PMU events we cannot test this feature. >> >>> >>> >>> This looks pretty, but let's keep exporting verified data. >>> > I just wanted to revisit this patch series with some updates on > > Here is where the Android TV provides the cache details. > [1] https://androidpctv.com/comparative-amlogic-s922x/ > > Amlogic S922X Hexa Core SoC has four ARM Cortex-A73 cores capable of > reaching 1.8Ghz > with 1MB L2 cache + 2 Cortex-A53 RAM processors with 256k L2 cache, > > https://boardor.com/blog/understanding-the-architecture-of-arm-cortex-a53-cache > > Also Amlogic A311D processor utilizes a "big.LITTLE" architecture, combining: > > Quad-core ARM Cortex-A73: > Each Cortex-A73 core has: > 64 KB L1 instruction cache 64 KB L1 data cache > The Cortex-A73 cluster shares a 1 MB unified L2 cache. > > Dual-core ARM Cortex-A53: > Each Cortex-A53 core has: > 32 KB L1 instruction cache, 32 KB L1 data cache > > The Cortex-A53 cluster shares a 512 KB unified L2 cache. > > From what I understand, CPU caches are a core feature of the CPU. > Do you think I should update these patches and resend ? Yes sure, Neil > > Thanks > -Anand