From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: will@kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org,
mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com,
catalin.marinas@arm.com, saiprakash.ranjan@codeaurora.org,
dianders@chromium.org, kernel-team@android.com
Subject: Re: [PATCH 7/8] arm64: cpufeature: Relax checks for AArch32 support at EL[0-2]
Date: Wed, 15 Apr 2020 12:37:31 +0100 [thread overview]
Message-ID: <d1f538ec-e956-c136-d0f8-54e7351a28a9@arm.com> (raw)
In-Reply-To: <20200415105843.GE12621@willie-the-truck>
On 04/15/2020 11:58 AM, Will Deacon wrote:
> On Wed, Apr 15, 2020 at 11:50:58AM +0100, Suzuki K Poulose wrote:
>> On 04/14/2020 10:31 PM, Will Deacon wrote:
>>> We don't need to be quite as strict about mismatched AArch32 support,
>>> which is good because the friendly hardware folks have been busy
>>> mismatching this to their hearts' content.
>>>
>>> * We don't care about EL2 or EL3 (there are silly comments concerning
>>> the latter, so remove those)
>>>
>>> * EL1 support is gated by the ARM64_HAS_32BIT_EL1 capability and handled
>>> gracefully when a mismatch occurs
>>>
>>> * EL1 support is gated by the ARM64_HAS_32BIT_EL0 capability and handled
>>
>> s/EL1/EL0
>>
>>> gracefully when a mismatch occurs
>>>
>>> Relax the AArch32 checks to FTR_NONSTRICT.
>>
>> Agreed. We should do something similar for the features exposed by the
>> ELF_HWCAP, of course in a separate series.
>
> Hmm, I didn't think we needed to touch the HWCAPs, as they're derived from
> the sanitised feature register values. What am I missing?
sorry, that was cryptic. I was suggesting to relax the ftr fields to
NONSTRICT for the fields covered by ELF HWCAPs (and other CPU hwcaps).
Suzuki
next prev parent reply other threads:[~2020-04-15 11:33 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 21:31 [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Will Deacon
2020-04-14 21:31 ` [PATCH 1/8] arm64: cpufeature: Relax check for IESB support Will Deacon
2020-04-15 10:02 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 2/8] arm64: cpufeature: Spell out register fields for ID_ISAR4 and ID_PFR1 Will Deacon
2020-04-15 10:09 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 3/8] arm64: cpufeature: Add CPU capability for AArch32 EL1 support Will Deacon
2020-04-15 8:55 ` Marc Zyngier
2020-04-15 17:00 ` Will Deacon
2020-04-15 10:13 ` Suzuki K Poulose
2020-04-15 10:14 ` Will Deacon
2020-04-15 13:15 ` Suzuki K Poulose
2020-04-15 13:22 ` Marc Zyngier
2020-04-17 9:44 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 4/8] arm64: cpufeature: Remove redundant call to id_aa64pfr0_32bit_el0() Will Deacon
2020-04-15 10:25 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 5/8] arm64: cpufeature: Factor out checking of AArch32 features Will Deacon
2020-04-15 10:36 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only Will Deacon
2020-04-15 10:43 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 7/8] arm64: cpufeature: Relax checks for AArch32 support at EL[0-2] Will Deacon
2020-04-15 10:50 ` Suzuki K Poulose
2020-04-15 10:58 ` Will Deacon
2020-04-15 11:37 ` Suzuki K Poulose [this message]
2020-04-15 12:29 ` Will Deacon
2020-04-17 9:37 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 8/8] arm64: cpufeature: Add an overview comment for the cpufeature framework Will Deacon
2020-04-16 11:58 ` Will Deacon
2020-04-16 14:59 ` Suzuki K Poulose
2020-04-16 15:26 ` Marc Zyngier
2020-04-16 18:12 ` Will Deacon
2020-04-16 8:39 ` [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Sai Prakash Ranjan
2020-04-16 10:26 ` Sai Prakash Ranjan
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