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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36dd85a5464sm2052690eec.4.2026.11.04.14.47.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Nov 2026 14:47:33 -0800 (PST) Message-ID: Date: Wed, 4 Nov 2026 14:47:32 -0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] dt-bindings: phy: qcom: Add common qcom,csi2-phy To: Bryan O'Donoghue Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261103214105.3605181-1-anusha.nandi@oss.qualcomm.com> <20261103214105.3605181-2-anusha.nandi@oss.qualcomm.com> <803d16ba-49c9-404c-8973-e4d4dc02b1e3@kernel.org> Content-Language: en-US From: Anusha Arun Nandi In-Reply-To: <803d16ba-49c9-404c-8973-e4d4dc02b1e3@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA0MDA4OSBTYWx0ZWRfX+a1WnGIoWx66 IXKzyYArpeDq/iLqWoHDG9D8FWcPvsvRvoBz0rUfaKx3dFu8lEKC0RIULTV3fXLPJfLFAL3txu+ JA0g+BpDEDs8n5QhIKuq2fxAzXZ88PSac0z/hWiedR8C1RTMsr+9PqyRyKSoGO7HU1OUj2fhLwl btDvRDdQfFxQxOWGkWim1K2lNt0fL+rUk6IVMqVqlK1L4OE5koRSJEPTNs052dlSflnuHdPCwIh LwVG8mtvmRA8IAr96ebbtTLGu+oIrN3UQWUIM/A4nTi8qTxn4YXdu9wxAT1BjKf+9bgQbSx4uKa KL4OR664c+SNwphB6TqDKS7ZIg6HtiP88hGxIYf9YeHysIZ2t9rxALnQQ4ooruSwTuUu83mX2a4 pXmNDSq4xgjCvL64p0Umcv4QJRcl74iX5HhP8MKHwXrK8LArwMAjrfxFn3XiiE4qOhtXq4fa5D/ q69JcgMdSyIy1fe+KiA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA0MDA4OSBTYWx0ZWRfX5MfT69smn5F8 S39LPx1jhFXpMfOB240CMYzEcgR9mWKstFZM2vJMU0NFDWypZwQ+5dP06Rm9T6TnrDUIJKvXgvc ydosjAsFvVBHzdE4xk4dhLjKq9CmOq4= X-Proofpoint-GUID: DUzgwAl8kcWmLs62j7wroQB_FQ5tRhmu X-Proofpoint-ORIG-GUID: DUzgwAl8kcWmLs62j7wroQB_FQ5tRhmu X-Authority-Analysis: v=2.4 cv=futJ914f c=1 sm=1 tr=0 ts=6aebb607 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=YckT5oapyQZYSsRhpqkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-04_05,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 suspectscore=0 bulkscore=0 spamscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611040089 On 11/4/2026 3:29 AM, Bryan O'Donoghue wrote: > On 03/11/2026 21:41, Anusha Arun Nandi wrote: >> SA8775P, QCS8300 and SC7280 CSI2 PHYs are bit-for-bit identical in >> devicetree shape (ports, bus-type, data-lanes, operating-points-v2, >> clocks, single "top" power-domain, vdda-phy/vdda-pll supplies). >> >> Describe all three with a single qcom,csi2-phy.yaml and a compatible >> oneOf, rather than one standalone schema per SoC. QCS8300 is further >> required to be paired with a qcom,sa8775p-csi2-phy fallback >> compatible, the same way other Qualcomm bindings express full >> hardware compatibility between two SoCs (see qcom,qusb2-phy.yaml); >> this lets the driver bind QCS8300 nodes via its qcom,sa8775p-csi2-phy >> match entry rather than carrying a duplicate one. >> >> qcom,x1e80100-csi2-phy.yaml is a separate PHY with a different shape >> (3 clocks, 3 power-domains, different supply names, DPHY split-mode >> support) and is left untouched. >> >> Reviewed-by: Jigarkumar Zala >> Signed-off-by: Anusha Arun Nandi >> --- >>   .../bindings/phy/qcom,csi2-phy.yaml           | 176 ++++++++++++++++++ >>   1 file changed, 176 insertions(+) >>   create mode 100644 Documentation/devicetree/bindings/phy/qcom,csi2- >> phy.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml >> b/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml >> new file mode 100644 >> index 000000000000..5d25547528bd >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml >> @@ -0,0 +1,176 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +# Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights >> reserved. >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/qcom,csi2-phy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm CSI2 PHY >> + >> +maintainers: >> +  - Anusha Arun Nandi >> + >> +description: >> +  Qualcomm MIPI CSI2 D-PHY. Connects MIPI CSI2 sensors to Qualcomm's >> Camera >> +  CSI Decoder. >> + >> +properties: >> +  compatible: >> +    oneOf: >> +      - enum: >> +          - qcom,sa8775p-csi2-phy >> +          - qcom,sc7280-csi2-phy >> +      - items: >> +          - enum: >> +              - qcom,qcs8300-csi2-phy >> +          - const: qcom,sa8775p-csi2-phy >> + >> +  reg: >> +    maxItems: 1 >> + >> +  clocks: >> +    maxItems: 2 >> + >> +  clock-names: >> +    items: >> +      - const: core >> +      - const: timer >> + >> +  interrupts: >> +    maxItems: 1 >> + >> +  operating-points-v2: true >> + >> +  opp-table: >> +    type: object >> + >> +  power-domains: >> +    items: >> +      - description: Titan Top GDSC - Titan ISP Block, Global >> Distributed Switch Controller. >> + >> +  power-domain-names: >> +    items: >> +      - const: top >> + >> +  vdda-phy-supply: >> +    description: Phandle to PHY supply. >> + >> +  vdda-pll-supply: >> +    description: Phandle to PLL supply. > > Why are we departing from vdda-0p9-supply and vdda-1p2-supply ? > > Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml > The 0p9 and 1p2 supply names are derived from the current CSIPHY hardware power rail naming, which may not remain consistent across future platforms. To make the binding more generic and function-oriented, I will rename them to vdda-hs-supply and vdda-lp-supply, which better represent the CSIPHY power requirements.>> + >> +  ports: >> +    $ref: /schemas/graph.yaml#/properties/ports >> + >> +    properties: >> +      port@0: >> +        $ref: /schemas/graph.yaml#/$defs/port-base >> +        description: >> +          Sensor input. A single sensor is described by a single >> endpoint >> +          with one to four data lanes, numbered 1-4. The clock lane is >> +          position 0. > > Since you've cloned and owned the yaml - you've also dropped the > description of DPHY split mode. > Thank you for highlighting. I will add the support for it. >> + >> +        unevaluatedProperties: false >> + >> +        properties: >> +          endpoint: >> +            $ref: /schemas/media/video-interfaces.yaml# >> +            unevaluatedProperties: false >> +            properties: >> +              bus-type: >> +                enum: >> +                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY >> +                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY >> +                default: 4 >> + >> +              data-lanes: >> +                minItems: 1 >> +                maxItems: 4 >> +                items: >> +                  minimum: 1 >> +                  maximum: 4 >> +                description: >> +                  Data lane positions following this endpoint's clock >> +                  lane. Positions are a per-port logical numbering, not >> +                  package pad or ball positions. >> + >> +            required: >> +              - data-lanes >> +              - remote-endpoint > > And then you've dropped the DPHY split mode defintion > > NAK > > Please either clone and own the whole DPHY split-mode circus or just > modify the existing definition to include your new stuff. > Will be modified along with other comments for v2 version, sending in shortly.>> + >> +      port@1: >> +        $ref: /schemas/graph.yaml#/properties/port >> +        description: Output to the CAMSS CSID controller. >> + >> +    required: >> +      - port@0 >> +      - port@1 >> + >> +required: >> +  - compatible >> +  - reg >> +  - clocks >> +  - clock-names >> +  - interrupts >> +  - operating-points-v2 >> +  - power-domains >> +  - power-domain-names >> +  - vdda-phy-supply >> +  - vdda-pll-supply >> +  - ports >> + >> +additionalProperties: false >> + >> +examples: >> +  - | >> +    #include >> +    #include >> +    #include >> + >> +    phy@ac9c000 { >> +        compatible = "qcom,sa8775p-csi2-phy"; >> +        reg = <0x0ac9c000 0x2000>; >> + >> +        clocks = <&camcc CAM_CC_CSIPHY0_CLK>, >> +                 <&camcc CAM_CC_CSI0PHYTIMER_CLK>; >> +        clock-names = "core", >> +                      "timer"; >> + >> +        interrupts = ; >> + >> +        operating-points-v2 = <&csiphy_opp_table>; >> + >> +        power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; >> +        power-domain-names = "top"; >> + >> +        vdda-phy-supply = <&vreg_l4a>; >> +        vdda-pll-supply = <&vreg_l1c>; >> + >> +        ports { >> +            #address-cells = <1>; >> +            #size-cells = <0>; >> + >> +            port@0 { >> +                reg = <0>; >> +                csiphy0_in: endpoint { >> +                    bus-type = ; >> +                    data-lanes = <1 2 3 4>; >> +                    remote-endpoint = <&sensor_out>; >> +                }; >> +            }; >> + >> +            port@1 { >> +                reg = <1>; >> +                csiphy0_out: endpoint { >> +                    remote-endpoint = <&csid_in>; >> +                }; >> +            }; >> +        }; >> + >> +        csiphy_opp_table: opp-table { >> +            compatible = "operating-points-v2"; >> + >> +            opp-300000000 { >> +                opp-hz = /bits/ 64 <300000000>; >> +            }; >> +        }; >> +    }; >> -- >> 2.34.1 >