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Sat, 20 Dec 2025 08:04:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IEYoKASIiDh1XJqI3CeJmoab/jilojA4jpnJzSooOYAC3DFbkpG6RKX+gYwN338b4mcKlBF2g== X-Received: by 2002:a05:7022:6290:b0:11d:f440:b758 with SMTP id a92af1059eb24-121722de94dmr8504956c88.25.1766246693981; Sat, 20 Dec 2025 08:04:53 -0800 (PST) Received: from [192.168.1.57] ([98.148.145.183]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1217253c058sm22486533c88.11.2025.12.20.08.04.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 20 Dec 2025 08:04:52 -0800 (PST) Message-ID: Date: Sat, 20 Dec 2025 08:04:51 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali To: Bryan O'Donoghue , Vladimir Zapolskiy , Konrad Dybcio , Hangxiang Ma , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Mauro Carvalho Chehab Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, Jingyi Wang , Atiya Kailany References: <20251113-add-support-for-camss-on-kaanapali-v6-0-1e6038785a8e@oss.qualcomm.com> <20251113-add-support-for-camss-on-kaanapali-v6-1-1e6038785a8e@oss.qualcomm.com> <37d0f89f-69be-45a7-90fa-347d6a3800bf@oss.qualcomm.com> <2d7ac7e8-ab69-44a6-b732-3657abf3a5a6@oss.qualcomm.com> <2ce4e296-701a-4354-8988-87525769ccac@linaro.org> Content-Language: en-US From: Vijay Kumar Tumati In-Reply-To: <2ce4e296-701a-4354-8988-87525769ccac@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: qJ6E2pd7Q2oiTlYonLn-CtFB0_XZgd7Y X-Proofpoint-GUID: qJ6E2pd7Q2oiTlYonLn-CtFB0_XZgd7Y X-Authority-Analysis: v=2.4 cv=CeEFJbrl c=1 sm=1 tr=0 ts=6946c927 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=BiHMn5M11h/vNwziJwzFrg==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=6gem9hBlJlRA9BxbBQ8A:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIwMDEzOSBTYWx0ZWRfX4CahMsBn/N9g xWT+a65SzlTUBqlyvpjhIdH0eLPLrhXSFp35EN33dt8Ifig7mFByLVAF0YXxI0F9vj7XCe9pY08 PZ5wdqxRPFJ5k7pJKG0oHDjtZJCZFj52Vh7LX7YRSQ1i/8FhcqCLTFoQthJPPeZKktlyL5dcysz CXPogW4R7DDKA9WMwhHi3KliPZDTSskXAgqddCpFGmvVkYo5D+nq1DlqkI596rXdSQyypTBiq2B /kqNfJZ8nO3GjNBgnTMhtKbS9GN1tvY4CZ1OzHiVfCqSuQNsMD47gXu30prVjR7emRTklfXFYbM 8yC+gKeQLogKtDGjPkI3CXGOC0iJ7SkRkN+FbNR4h/0BTNRr8JZ7EIKnKKMg85Q1e296lgH3XKV XUNhT7FnX/rlWHEAVWNPv6R5v/T0GV2r7rTb6nrX/Teq/hjlwuf2HuXn8jxrb4SRPuAeOH/zzSI cmD4zQ0/677StB3LN6w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-20_03,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512200139 On 12/16/2025 7:29 PM, Bryan O'Donoghue wrote: > On 17/12/2025 00:46, Vijay Kumar Tumati wrote: >>> I don't understand a reason why to do worse for the upstream, when >>> there is >>> a clear and feasible alternative not to do worse, thus my >>> misunderstanding >>> and my grief for upstream CAMSS are my concerns. >>> >> Thanks for the comments, Vladimir. Bryan's and Krzysztof's argument >> was that the bindings are required to describe the full hardware >> regardless of the driver support and either way not modifiable in the >> future, so they preferred having the HW properties of the key >> functional blocks in the bindings. And we were specifically asked to >> add the properties into this node in this patch series. Having said >> that, my knowledge on how the bindings are handled upstream in the >> long run as the requirements evolve, is limited. So I will look for >> some expert advise from Bryan here as he strongly advised for these. >> Thanks again. > > I see no technical reason why describing the whole hardware block > precludes any further work. How could it ? > > Anyway, I'll repeat my ask to describe: > > - The full register set > - The interconnects > - The clocks and resets > - The SIDs > > --- > bod Yes, it is what's been done. Assuming this thread is closed then. Thanks, Vijay.