From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 589FCC77B7A for ; Wed, 7 Jun 2023 11:03:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238971AbjFGLDX (ORCPT ); Wed, 7 Jun 2023 07:03:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239898AbjFGLDB (ORCPT ); Wed, 7 Jun 2023 07:03:01 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 194E926AE; Wed, 7 Jun 2023 04:02:00 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 61238AB6; Wed, 7 Jun 2023 04:01:40 -0700 (PDT) Received: from [10.57.75.6] (unknown [10.57.75.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3511D3F663; Wed, 7 Jun 2023 04:00:49 -0700 (PDT) Message-ID: Date: Wed, 7 Jun 2023 12:00:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH 01/32] perf: Allow a PMU to have a parent Content-Language: en-GB To: Peter Zijlstra , Mark Rutland Cc: Jonathan Cameron , Yicong Yang , Ingo Molnar , Arnaldo Carvalho de Melo , Will Deacon , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, gregkh@linuxfoundation.org, yangyicong@hisilicon.com, linuxarm@huawei.com, Dan Williams , Shaokun Zhang , Jiucheng Xu , Khuong Dinh , Robert Richter , Atish Patra , Anup Patel , Andy Gross , Bjorn Andersson , Frank Li , Shuai Xue , Vineet Gupta , Shawn Guo , Fenghua Yu , Dave Jiang , Wu Hao , Tom Rix , linux-fpga@vger.kernel.org, Suzuki K Poulose , Liang Kan References: <20230404134225.13408-1-Jonathan.Cameron@huawei.com> <20230404134225.13408-2-Jonathan.Cameron@huawei.com> <61f8e489-ae76-38d6-2da0-43cf3c17853d@huawei.com> <20230406111607.00007be5@Huawei.com> <20230406124040.GD392176@hirez.programming.kicks-ass.net> <20230406174445.0000235c@Huawei.com> <20230406194938.GB405948@hirez.programming.kicks-ass.net> <20230606131859.GC905437@hirez.programming.kicks-ass.net> <20230606134816.GF905437@hirez.programming.kicks-ass.net> From: Robin Murphy In-Reply-To: <20230606134816.GF905437@hirez.programming.kicks-ass.net> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2023-06-06 14:48, Peter Zijlstra wrote: > On Tue, Jun 06, 2023 at 02:30:52PM +0100, Mark Rutland wrote: > >>>> Uh, *which* CPU device? Do we have a container device for all CPUs? >>> >>> drivers/base/cpu.c:per_cpu(cpu_sys_devices, cpu) for whatever the core >>> pmu is for that cpu ? >> >> ... but the struct pmu covers several CPUs, so I don't have a single 'cpu', no? >> >> If I have a system where cpu{0,1,2} are Cortex-A53 and cpu{3,4} are Cortex-A57, >> I have two struct pmu instances, each associated with several CPUs. When I >> probe each of those I determine a cpumask for each. > > Bah :/ Clearly I overlooked the disparity there. > >>>>>> My overall favorite is an l2 cache related PMU that is spun up in >>>>>> arch/arm/kernel/irq.c init_IRQ() >>>> >>>> That's an artifact of the L2 cache controller driver getting initialized there; >>>> ideally we'd have a device for the L2 cache itself (which presumably should >>>> hang off an aggregate CPU device). >>> >>> /sys/devices/system/cpu/cpuN/cache/indexM >>> >>> has a struct device somewhere in >>> drivers/base/cacheinfo.c:ci_index_dev or somesuch. >> >> I guess, but I don't think the L2 cache controller (the PL310) is actually tied >> to that today. > > All it would do is make fancy links in sysfs I think, who cares ;-) > >>>>> Yeah, we're going to have a ton of them as well. Some of them are PCI >>>>> devices and have a clear parent, others, not so much :/ >>>> >>>> In a number of places the only thing we have is the PMU driver, and we don't >>>> have a driver (or device) for the HW block it's a part of. Largely that's >>>> interconnect PMUs; we could create container devices there. >>> >>> Dont they have a PCI device? But yeah, some are going to be a wee bit >>> challenging. >> >> The system might not even have PCI, so it's arguable that they should just hang >> off an MMIO bus (which is effectively what the platofrm bus is). > > You and your dodgy platforms :-) For system PMUs we'll pretty much always have a platform device corresponding to a DT/ACPI entry used to describe MMIO registers and/or interrupts. In many cases the PMU is going to be the only part of the underlying device that is meaningful to Linux anyway, so I don't see any issue with just hanging the PMU device off its corresponding platform device - it still gives the user a way to map a PMU instance back to some understandable system topology (i.e. ACPI/DT) to disambiguate, and that's the most important thing. Thanks, Robin.