From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mta0.migadu.com (out-6.mta0.migadu.com [91.218.175.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA80A47124D for ; Wed, 16 Sep 2026 08:40:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.6 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789548053; cv=none; b=XvFamOo3pZzUboJEwFr/u4g1UB6wfIA61pHC28DWCS2ld8nx55I4EL+lYZ0lcDt1frmf4AhGSXb3O/sq5jNI9UgFBLCARlMV//kCmfCDcKBkkcol7cl9Wvy/6+ZYhB4T5hnHKWkOlqdGj39C60JHfKnWFzvsFLSj5IqT1rfl7VE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789548053; c=relaxed/simple; bh=FhrTUCd/cVH8OoVyad9tP9zVOBg5mMP7ZPaAcgmccV4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Z/ZvnyFDPdfidjynF4SlnsgkW+Ns/+f0Bv/VTHuyj9aqf8sTrCxS0A0DVlvw7AlbS4F+AIMQGuznZmeWvIc61Fp+GxbCfnyBBzZrmPuRZ/WNkDhrTSS5ZyviW5lXfi71ILTGUIDYGL6G7Ih6roZrdeFPYoveod+2insmqSDAfvA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Z14n6AO8; arc=none smtp.client-ip=91.218.175.6 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Z14n6AO8" X-Envelope-To: linux-kernel@vger.kernel.org DKIM-Signature: a=rsa-sha256; bh=FhrTUCd/cVH8OoVyad9tP9zVOBg5mMP7ZPaAcgmccV4=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1789548048; v=1; x=1790152848; b=Z14n6AO8qkfBp86t4Gm46sWpqIlvYAfyZfVpPzzJiUzVdmfdNFvJaEOB1sMhi/NO6mF85lAx iojhbLRngx4alc45P+bj+EzbgtwvAsL5IfQMwheaYQQRL6rhRD97wQfDbDXRT5uGKKnc43xFjBz SAYVCrYnfEjJd4AWMw6iRoXs= X-Envelope-To: linux-kernel@vger.kernel.org Received: by smtp.migadu.com with ESMTPS id 6f5ce7a0d81dd4a7; Wed, 16 Sep 2026 08:40:42 +0000 X-Mizu-Trace-ID: 6f5ce7a0d81dd4a7 X-Migadu-Flow: FLOW_OUT Message-ID: Date: Wed, 16 Sep 2026 16:40:34 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v2 2/2] net: ethernet: oa_tc6: add reset-gpios support To: Alessandro Zini Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Parthiban Veerasooran , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni References: <20260916075349.21822-1-alessandro.zini@siemens.com> <20260916075349.21822-3-alessandro.zini@siemens.com> From: Qingfang Deng In-Reply-To: <20260916075349.21822-3-alessandro.zini@siemens.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, On 2026/9/16 15:53, Alessandro Zini wrote: > OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface specification > (v1.1, Section 8.2) defines an external RESET pin as an optional reset > source for the MAC-PHY. > > Add support for an optional reset GPIO in oa_tc6_init(). If specified in > the device tree, assert the hardware reset line for 10 us and allow 1 ms > settle time for crystal oscillator startup before performing the initial > TC6 control protection check and software reset. > > Suggested-by: Parthiban Veerasooran > Signed-off-by: Alessandro Zini > --- > Changes in v2: > - Moved reset GPIO handling from lan865x.c to common oa_tc6.c as suggested > by Parthiban Veerasooran. > > drivers/net/ethernet/oa_tc6.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c > index 6fcc5f561d560..a697e2cb99cd8 100644 > --- a/drivers/net/ethernet/oa_tc6.c > +++ b/drivers/net/ethernet/oa_tc6.c > @@ -11,6 +11,8 @@ > #include > #include > #include > +#include > +#include > > /* Control command header */ > #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) > @@ -88,6 +90,7 @@ struct oa_tc6 { > bool disable_traffic; > bool prot_ctrl; > enum oa_tc6_quirk_flag quirk_flags; > + struct gpio_desc *reset_gpio; > }; > > enum oa_tc6_header_type { > @@ -1503,6 +1506,24 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netdev, > if (!tc6->spi_data_rx_buf) > return NULL; > > + tc6->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", > + GPIOD_OUT_LOW); Please use GPIOD_OUT_HIGH here, so the reset pin is initially asserted, and the first gpiod_set_value_cansleep below can be removed. See function __mdiobus_register as an example. > + if (IS_ERR(tc6->reset_gpio)) { > + dev_err_probe(&spi->dev, PTR_ERR(tc6->reset_gpio), > + "Failed to get reset GPIO\n"); > + return NULL; > + } > + > + if (tc6->reset_gpio) { > + /* Assert hardware reset for 10 us (datasheet specifies min 5 us) > + * and allow 1 ms settle time for crystal oscillator startup. > + */ > + gpiod_set_value_cansleep(tc6->reset_gpio, 1); > + fsleep(10); > + gpiod_set_value_cansleep(tc6->reset_gpio, 0); > + fsleep(1000); > + } > + > /* Check the PROTE bit status so that we can reset the device */ > ret = oa_tc6_check_ctrl_protection(tc6); > if (ret) { Kind regards,